DCI—VRP Termination - DS985

The Kria SOM design leverages the AMD Zynq™ UltraScale+™ MPSoCs with InFO package (XCK24-UBVA530-2LV) for a physically smaller packaging and SOM size. This allows product development to reduce PCB size through internally controlling the impedance of I/O pins, removing the need for external termination resistors. DCI configuration is only used on HP I/O banks within the MPSoCs.

For more information on DCI, see the UltraScale Architecture SelectIO Resources User Guide (UG571), with specific attention to the DCI—Only Available in the HP I/O Banks and VRP External Resistance Design Migration Guidelines topics. The has two HP I/O banks. The following table defines the VRP configuration for each bank. The value of 240Ω was chosen based upon the previous references.