Power and Electrical

This section describes the power requirements, power-on sequence, power-on reset sequence, and power management functions.

Table 1. KD240 Starter Kit Power Specifications
Parameter	Description
DC input power	+12V, 3A
Recommended power adapter	The CUI Inc. SMI36-12-V-P6 adapter connected using a center-pin positive barrel connector (2.5 mm ID, 5.5 mm OD)
SOM supply	+5V, 3A (V_{CC_SOM})
SOM power telemetry	Current sense device (INA260) is available through the I2C bus address `0x40` to monitor the current on the V_{CC_SOM} power rail. Refer to the Kria KD240 Drives Starter Kit User Guide (UG1093) for the `xlnx_platformstats` application that is provided in the AMD pre-built images to read this information.
USB 3.0	5V, 900 mA per port (limited to 2.1A total)
microSD card	3.3V, 200 mA
Pmod interface from Digilent Inc.	3.3V, 100 mA
1-wire temperature sensor I/O	3.3V
1-wire temperature sensor power	3.3V, 100 mA
Single-ended encoder I/O	V_IH = 3.3V to 5.5V, V_IL = 0 to 1.8V
Single-ended encoder power	5V, 0.1A
Differential encoder I/O	V_IH = 2V to 5.5V, V_IL = 0 to 0.8V
Differential encoder power	5V, 0.1A
Torque sensor analog input	0.3V to 3.4V
Torque sensor power	4.5V, 400 mA, can support 350Ω and 120Ω passive strain gauges
Inverter Power Domain
DC link	33V 20A nominal, absolute maximum of 36.7V 30A ^{1, 2}. The DC link voltage and current measurements are available through readback of the 12-bit AD7352 ADC. ADC SCLK for DC link is connected to HPA12P_CLK ADC CS_N for DC link is connected to HPA13N DC link voltage data is read from HPA12N DC link current data is read from HPA13P
Interface voltage	Set by DC_LINK input
Interface current	Current based on safe operating area (SOA) of MOSFET. CSD18512 SOA < 40V, DC_LINK 36.7V maximum.¹ Refer to the CSD18512 data sheet for details and other design criteria surrounding the SOA.
Brake connector voltage	DC_LINK
Brake connector current	Current based on SOA of MOSFET. CSD18512 SOA < 40V, DC_LINK 36.7V maximum.¹ Refer to the CSD18512 data sheet for details and other design criteria surrounding the SOA.
3-phase inverter telemetry	Three phases of voltage and current sense are available through readback of the 12-bit AD7352 ADC. The three ADC are wired in parallel. With one ADC per phase, the AD7352 has dual, simultaneous sampling, allowing simultaneous readback of all three phases, both voltage and current. For further information, refer to the AD7352 data sheet. ADC SCLK fanout for phase ADCs are connected to HPA00_CCP_CLK ADC CS_N fanout for phase ADCs are connected to HPA03N Phase A voltage data is read from HPA00_CCN Phase A current data is read from HPA01P Phase B voltage data is read from HPA01N Phase B current data is read from HPA02P Phase C voltage data is read from HPA02N Phase C current data is read from HPA03P
Maximum voltage limited by TVS diode. Maximum current limited by fuse at DC_LINK input.

KD240 Starter Kit Power On Sequence

External power adapter supplies 12V power
On-board regulator generates 5V supply and provides power to other voltage regulators
SOM power rail (V_{CC_SOM}) is powered by a 5V supply
When the 5V regulator output voltage level is within the specified range and a power-good signal is asserted and the POWER_OFF_C2M_L signal is deasserted by the carrier card
SOM on board power on sequencing starts
Carrier card provides PS and PL V_CCO voltage rails after the SOM asserts the V_{CCOEN_PS_M2C} and V_{CCOEN_PL_M2C} signals

KD240 Starter Kit Power On Reset

The SOM reset signal (PS_POR_L) is held in reset until the PS_PGOOD signal is asserted.
To perform a hard reset on the SOM, use the reset push-button on the carrier card to assert the PS_POR_L signal.
All the PS and PL I/O device reset signals on the carrier card are held in reset until 25 ms after the PS and PL power domain are powered up and stable.