Product Details

Alveo U50 Data Center Accelerator Card Data Sheet: Alveo U50 Card Data Sheet (DS965)

Document ID
DS965
Release Date
2023-06-23
Revision
1.8 English
Table 1. Alveo U50/U50 LV Accelerator Card Product Details
Specification U50 Production 1 U50 LV Production 1
Product SKU A-U50-P00G-PQ-G A-U50-P00G-LV-G
Total electrical card load 2 75W 75W
Thermal cooling solution Passive Passive
Weight 300g – 325g 300g – 325g
Form factor Half height, half length Half height, half length
Network interface 1x QSFP28 (100 GbE) 1x QSFP28 (100 GbE)
Network clock precision IEEE 1588 IEEE 1588
PCIe interface 3, 4 Gen3 x16, Gen4 x8, CCIX Gen3 x16 5,6
HBM2 total capacity 8 GB 8 GB
HBM2 bandwidth 316 GB/s 7 316 GB/s 7
Look-up tables (LUTs) 872K 872K
Registers 1,743K 1,743K
DSP slices 5,952 5,952
Max. Dist. RAM 24.6 Mb 24.6 Mb
36 Kb block RAM 1344 (47.3 Mb) 1344 (47.3 Mb)
288 Kb UltraRAM 640 (180.0 Mb) 640 (180.0 Mb)
GTY transceivers 20 20
VCCINT supported VNOM (0.85V) VLOW (0.72V)
AMD Vitis™ Development Enviroment Yes Yes
Vitis platform Gen3 x16 XDMA, Gen3 x4 XDMA 8 Gen3 x4 XDMA 9
Vivado Design Suite Yes Yes
Target workloads Fintech, video, database, and computational storage Machine learning (ML) inference
Qualified for deployment Yes Yes
  1. The Alveo programmable cable (sold separately) is required for development access. The cable provides micro-USB support from a host PC to the maintenance connector and can be purchased from AMD (Alveo Accessories). For more information about this cable, refer to Alveo Programming Cable User Guide (UG1377).
  2. The Alveo U50/U50 LV card has separate power rails for FPGA fabric and HBM2 memory. Developers must ensure their designs do not draw too much power for each rail. More information can be found in Alveo U50 Data Center Accelerator Card Installation Guide (ds962).
  3. The PCIe interface can be configured to support a variety of link widths and speeds. The maximum is Gen3 (8 GT/s) x16, Gen4 (16 GT/s) x8 or CCIX operating at 16 GT/s x8. The PCIe interface can also be configured into dual x8 interfaces and connected to hosts that support PCIe bifurcation.
  4. This block operates in compatibility mode for 16.0 GT/s (Gen4) operation. Refer to UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213) for details on compatibility mode.
  5. The Alveo U50 LV card with VCCINT core voltage set to VLOW only supports Gen3 x4 platform shells.
  6. The A-U50-P00G-LV-G card requires a PCI Express x16 slot for the edge connector and a supply of 75W.
  7. The HBM2 power is limited to 10W from the PCIe 3.3V rail. The performance that can be achieved using HBM2 is limited by this power limit and varies between designs. The nominal bandwidth for HBM2 is 201 GB/s. Peak HBM2 bandwidth measured for the A-U50-P00G-LV-G and A-U50-P00G-PQ-G cards is 316 GB/s in the non-PCIe compliant specification.
  8. The A-U50-P00G-PQ-G card with VCCINT core voltage set to 0.85V supports PCIe Gen3 x4 deployment platform shells for the AMD video solution.
  9. The A-U50-P00G-LV-G card with VCCINT core voltage set to 0.72V supports PCIe Gen3 x4 deployment platform shells for the AMD Vitis AI solution.

The following figure shows the components within an Alveo U50/U50 LV production accelerator card.

Figure 1. U50/U50 LV Production Block Diagram