The AMD Alveo U50/U50 LV accelerator card is a custom-built UltraScale+ FPGA that runs optimally (and exclusively) on Alveo architecture. The Alveo U50/U50 LV card features the XCU50 FPGA, which uses AMD stacked silicon interconnect (SSI) technology to deliver breakthrough FPGA capacity, bandwidth, and power efficiency. This technology allows for increased density by combining multiple super logic regions (SLRs). The XCU50 comprises two SLRs with the bottom SLR (SLR0) integrating an HBM2 controller to interface with the adjacent 8 GB HBM2 memory.
The following figure shows the two SLR regions along with the connections for PCIe and SFP-QSFP. The HBM2 is co-located on the XCU50 device and connects directly to SLR0.
For customers using the Vitis application acceleration development flow, a platform is created that manages the PCIe interface, data transfers, and card status information. It also remotely loads kernels and performs a number of other functions. This platform is part of the static region (an area of the FPGA that is not reconfigurable). This platform consumes resources from the available resources listed in Table 1. The specific amount of resources depends on which platform, and even which version of a platform is used. For developing applications, refer to the Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).