Device Pin-to-Pin Output Parameter Guidelines - Device Pin-to-Pin Output Parameter Guidelines

Device Pin-to-Pin Output Parameter Guidelines - Device Pin-to-Pin Output Parameter Guidelines - DS960

Versal HBM Series Data Sheet: DC and AC Switching Characteristics (DS960)

Document ID

DS960

Release Date

2024-07-24

Revision

1.5 English

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.

Table 1. Global Clock Input to Output Delay With MMCM (Internal Mode)
Symbol	Description^{1, 2}	Device	Performance as a Function of Speed Grade and Operating Voltage (V_CCINT)					Units
			0.88V (H)	0.80V (M)		0.70V (L)
			-3	-2	-1	-2	-1
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM
T_ICKOFMMCM	Global clock input and output flip-flop with MMCM	XCVH1522	5.87	6.52	6.87	6.52	6.89	ns
		XCVH1542	5.87	6.52	6.87	6.52	6.89	ns
		XCVH1582	5.87	6.52	6.87	6.52	6.89	ns
		XCVH1742	5.87	6.52	6.87	6.52	6.89	ns
		XCVH1782	5.87	6.52	6.87	6.52	6.89	ns
This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net. MMCM output jitter is already included in the timing calculation.