PMC eMMC Controller Interface - PMC eMMC Controller Interface - DS959

Versal Premium Series Data Sheet: DC and AC Switching Characteristics (DS959)
Document_ID
DS959
Release_Date
2026-02-06
Revision
1.8 English
isSecure
false
Table 1. eMMC Controller Interface
Symbol Description 1 Min Max Units
eMMC Interface Standard Mode
FEMMCSCLK eMMC standard device clock frequency 2 – 25 MHz
TDCEMMCCLK eMMC clock duty cycle 45 55 %
TEMMCCKO Clock to output delay, all outputs –2.0 4.5 ns
TEMMCDCK Input setup time, all inputs 2.0 – ns
TEMMCCKD Input hold time, all inputs 2.0 – ns
eMMC Interface High-speed SDR Mode
FEMMCSDRCLK eMMC high-speed SDR device clock frequency 25 50 MHz
TDCEMMCSDRCLK eMMC high-speed SDR clock duty cycle 45 55 %
TEMMCSDRCKO Clock to output delay, all outputs 3 3.2 16.8 ns
TEMMCSDRDIVW Input valid data window 4 0.4 – UI
eMMC Interface High-speed DDR Mode
FEMMCDDRCLK eMMC high-speed DDR device clock frequency 25 50 MHz
TDCEMMCDDRCLK eMMC high-speed DDR clock duty cycle 45 55 %
TEMMCDDRCKO1 Data clock to output delay 3 2.7 7.3 ns
TEMMCDDRDIVW Input valid data window 4 0.35 – UI
TEMMCDDRCKO2 Command clock to output delay 3.2 16 ns
TEMMCDDRDCK2 Command input setup time 3.9 – ns
TEMMCDDRCKD2 Command input hold time 2.5 – ns
eMMC Interface HS200 Mode
FEMMCHS200CLK eMMC HS200 device clock frequency 25 200 MHz
TDCEMMCHS200CLK eMMC HS200 clock duty cycle 30 70 %
TEMMCHS200CKO Clock to output delay, all outputs 3 1.0 3.4 ns
TEMMCHS200DIVW Input valid data window 4 0.5 – UI
  1. The test condition settings for the eMMC modes are: 12 mA drive strength, fast slew rate, and a 15 pF load. The OTAP delay (OTAP_DLY[5:0] ) test condition settings are: eMMC high-speed SDR mode = 0x05, eMMC high-speed DDR mode = 0x05, and eMMC HS200 mode = 0x02.
  2. EMIO is supported in the eMMC standard mode.
  3. This specification is achieved using predetermined DLL tuning.
  4. This specification is required for capturing input data using DLL tuning.