SelectIO Levels

Versal AI Edge Series Data Sheet: DC and AC Switching Characteristics (DS958)
Document ID
DS958
Release Date
2024-11-22
Revision
1.10 English
Table 1. SelectIO DC Input and Output Levels For HDIO Banks
I/O Standard 1, 2 VIL VIH VOL VOH IOL IOH
V, Min V, Max V, Min V, Max V, Max V, Min mA mA
HSTL_I_18 –0.300 50% VCCO – 0.100 50% VCCO + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 8.0 –8.0
LVCMOS18 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO – 0.450 Note 3 Note 3
LVCMOS25 –0.300 0.700 1.700 VCCO + 0.300 0.400 VCCO – 0.400 Note 3 Note 3
LVCMOS33 –0.300 0.800 2.000 3.400 0.400 VCCO – 0.400 Note 3 Note 3
LVTTL –0.300 0.800 2.000 3.400 0.400 2.400 Note 3 Note 3
SSTL18_I –0.300 50% VCCO – 0.125 50% VCCO + 0.125 VCCO + 0.300 VCCO/2 – 0.470 VCCO/2 + 0.470 8.0 –8.0
  1. Tested according to relevant specifications.
  2. Standards specified using the default I/O standard configuration. For details, see the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).
  3. Supported drive strengths of 4, 8, or 12 mA in HDIO banks.
Table 2. SelectIO DC Input and Output Levels for XPIO Banks
I/O Standard 1, 2, 3 VIL VIH VOL VOH IOL IOH
V, Min V, Max V, Min V, Max V, Max V, Min mA mA
HSTL_I –0.300 50% VCCO – 0.100 50% VCCO + 0.100 VCCO + 0.300 0.400 VCCO – 0.400 5.8 –5.8
HSTL_I_12 –0.300 50% VCCO – 0.080 50% VCCO + 0.080 VCCO + 0.300 25% VCCO 75% VCCO 4.1 –4.1
HSUL_12 –0.300 50% VCCO – 0.130 50% VCCO + 0.130 VCCO + 0.300 20% VCCO 80% VCCO 0.1 –0.1
LVCMOS12 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.400 VCCO – 0.400 Note 4 Note 4
LVCMOS15 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO – 0.450 Note 5 Note 5
LVDCI_15 –0.300 35% VCCO 65% VCCO VCCO + 0.300 0.450 VCCO – 0.450 7.0 –7.0
SSTL12 –0.300 50% VCCO – 0.100 50% VCCO + 0.100 VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150 8.0 –8.0
SSTL135 –0.300 50% VCCO – 0.090 50% VCCO + 0.090 VCCO + 0.300 VCCO/2 – 0.150 VCCO/2 + 0.150 9.0 –9.0
SSTL15 –0.300 50% VCCO – 0.100 50% VCCO + 0.100 VCCO + 0.300 VCCO/2 – 0.175 VCCO/2 + 0.175 10.0 –10.0
  1. Tested according to relevant specifications.
  2. Standards specified using the default I/O standard configuration. For details, see the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).
  3. POD10 and POD12 DC input and output levels are shown in Table 3, Table 8, and Table 9.
  4. Supported drive strengths of 2, 4, 6, or 8 mA in XPIO banks.
  5. Supported drive strengths of 2, 4, 6, 8, or 12 mA in XPIO banks.
Table 3. DC Input Levels for Single-ended POD10, POD12, LVSTL06_12, and LVSTL_11 I/O Standards
I/O Standard 1, 2 VIL VIH
V, Min V, Max V, Min V, Max
POD10 –0.300 70% VCCO – 0.068 70% VCCO + 0.068 VCCO + 0.300
POD12 –0.300 70% VCCO – 0.068 70% VCCO + 0.068 VCCO + 0.300
LVSTL06_12 –0.300 VCCO/8 – 0.100 VCCO/8 + 0.100 VCCO + 0.300
LVSTL_11 –0.300 VCCO/6 – 0.100 VCCO/6 + 0.100 VCCO + 0.300
  1. Tested according to relevant specifications.
  2. Standards specified using the default I/O standard configuration. For details, see the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).
Table 4. Differential SelectIO DC Input and Output Levels for MIPI_DPHY
I/O Standard VICM (V) 1 VID (V) 2 VILHS 3 VIHHS 3 VOCM (V) 4 VOD (V) 5
Min Typ Max Min Typ Max Min Max Min Typ Max Min Typ Max
MIPI_DPHY for operation <1.5 GB/s 7 0.070 – 0.330 0.070 – – –0.040 0.460 0.150 0.200 0.250 0.140 0.200 0.270
MIPI_DPHY for operation at >1.5G GB/s 7 0.070 – 0.330 0.040 – – –0.040 0.460 0.150 0.200 0.250 0.140 0.200 0.270
  1. VICM is the input common mode voltage.
  2. VID is the input differential voltage (Q – Q).
  3. VIHHS and VILHS are the single-ended input high and low voltages, respectively.
  4. VOCM is the output common mode voltage.
  5. VOD is the output differential voltage (Q – Q).
  6. LVDS15 is specified in Table 1.
  7. High-speed option for MIPI_DPHY. The VID maximum is aligned with the standard’s specification. A higher VID is acceptable as long as the VIN specification is also met.
Table 5. Complementary Differential SelectIO DC Input and Output Levels for HDIO Banks
I/O Standard VICM (V) 1 VID (V) 2 VOL (V) 3 VOH (V) 4 IOL IOH
Min Typ Max Min Max Max Min mA mA
DIFF_HSTL_I_18 0.300 0.900 1.425 0.100 – 0.400 VCCO – 0.400 8.0 –8.0
DIFF_SSTL18_I 0.300 0.900 1.425 0.100 – (VCCO/2) – 0.47 (VCCO/2) + 0.47 8.0 –8.0
LVDS_25 0.300 1.200 1.425 0.100 0.600 – – – –
SUB_LVDS 0.500 0.900 1.300 0.070 – – – – –
LVPECL 0.300 1.200 1.425 0.100 0.600 – – – –
SLVS_400_25 0.070 0.200 0.330 0.140 0.450 – – – –
  1. VICM is the input common mode voltage.
  2. VID is the input differential voltage (Q – Q).
  3. VOL is the single-ended low-output voltage.
  4. VOH is the single-ended high-output voltage.
Table 6. Complementary Differential SelectIO DC Input and Output Levels for XPIO Banks
I/O Standard 1 VICM (V) 2 VID (V) 3 VOL (V) 4 VOH (V) 5 IOL IOH
Min Typ Max Min Max Max Min mA mA
DIFF_HSTL_I 0.680 VCCO/2 (VCCO/2) + 0.150 0.100 – 0.400 VCCO – 0.400 5.8 –5.8
DIFF_HSTL_I_12 0.400 x VCCO VCCO/2 0.600 x VCCO 0.100 – 0.250 x VCCO 0.750 x VCCO 4.1 –4.1
DIFF_HSUL_12 (VCCO/2) – 0.120 VCCO/2 (VCCO/2) + 0.120 0.100 – 20% VCCO 80% VCCO 0.1 –0.1
DIFF_SSTL12 (VCCO/2) – 0.150 VCCO/2 (VCCO/2) + 0.150 0.100 – (VCCO/2) – 0.150 (VCCO/2) + 0.150 8.0 –8.0
DIFF_SSTL135 (VCCO/2) – 0.150 VCCO/2 (VCCO/2) + 0.150 0.100 – (VCCO/2) – 0.150 (VCCO/2) + 0.150 9.0 –9.0
DIFF_SSTL15 (VCCO/2) – 0.175 VCCO/2 (VCCO/2) + 0.175 0.100 – (VCCO/2) – 0.175 (VCCO/2) + 0.175 10.0 –10.0
  1. DIFF_POD10 and DIFF_POD12 XPIO bank specifications are shown in Table 7, Table 8, and Table 9.
  2. VICM is the input common mode voltage.
  3. VID is the input differential voltage.
  4. VOL is the single-ended low-output voltage.
  5. VOH is the single-ended high-output voltage.
Table 7. DC Input Levels for Differential POD10, POD12, LVSTL06_12, and LVSTL_11 I/O Standards
I/O Standard 1, 2 VICM (V) VID (V)
Min Typ Max Min Max
DIFF_POD10 0.630 0.700 0.770 0.140 –
DIFF_POD12 0.756 0.840 0.924 0.160 –
DIFF_LVSTL06_12 0.143 0.150 0.157 0.140 –
DIFF_LVSTL_11 0.174 0.183 0.193 0.140 –
  1. Tested according to relevant specifications.
  2. Standards specified using the default I/O standard configuration. For details, see the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).
Table 8. DC Output Levels for Single-ended and Differential POD10, POD12, LVSTL06_12, and LVSTL_11 I/O Standards
I/O Standard Symbol Description 1, 2, 3 VOUT Min Typ Max Units
POD10 and POD12 ROL Pull-down resistance VOM_DC (as described in Table 9) 32 40 48 Ω
ROH Pull-up resistance VOM_DC (as described in Table 9) 32 40 48 Ω
LVSTL06_12 ROL Pull-down resistance VOCM_DC_LOW 32 40 48 Ω
ROH Pull-up resistance VOCM_DC_HIGH 32 40 48 Ω
LVSTL_11 (VOH = 50) ROL Pull-down resistance VOM_DC (as described in Table 9) 32 40 48 Ω
ROH Pull-up resistance VOM_DC (as described in Table 9) 32 40 48 Ω
  1. Tested according to relevant specifications.
  2. The tolerance limits are specified after calibration with stable voltage and temperature.
  3. Standards specified using the default I/O standard configuration. For details, see the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).
Table 9. Definitions for DC Output Levels for Single-ended and Differential POD10, POD12, LVSTL06_12, and LVSTL_11 I/O Standards
I/O Standard Symbol Description All Speed Grades Units
POD10 and POD12 VOM_DC DC output mid measurement level (for IV curve linearity) 0.8 x VCCO V
LVSTL_11 (VOH = 50) VOM_DC DC output mid measurement level (for IV curve linearity) VCCO/2 V
LVSTL06_12 VOCM_DC_LOW DC output mid measurement level (for IV curve linearity), drive logic Low VCCO/2 V
VOCM_DC_HIGH DC output measurement level (for IV curve linearity), drive logic High VCCO/2 to VCCO/4 V