Revision History

Versal AI Edge Series Data Sheet: DC and AC Switching Characteristics (DS958)

Document ID
DS958
Release Date
2024-04-30
Revision
1.7 English

The following table shows the revision history for this document.

Section Revision Summary
4/30/2024 Version 1.7
General updates

Updated Table 1 for production release:

  • XCVE2002 and XCVE2102 devices in speed grades -2MSE, -2MLE, -2MSI, -2MLI, -2LSE, -2LLE, -2LLI, -1MSE, -1MSI, -1MLI, -1LSE,  -1LSI, and -1LLI using the Vivado Design Suite 2023.2.2 v2.00.
  • XCVE2602, XCVE2802 devices in speed grade -2HP using the Vivado Design Suite 2023.2.2 v2.01.

This includes updates to the following tables:

Recommended Operating Conditions Updated VGTYP_AVCC with voltages based upon temperature ranges (E, I, Q, or M).
Device Identification Updated XCVE2302 and XCVE2802 device ID codes.
DDR4 and LPDDR4/4X Memory Interface Controller Updated Note 5.
Table 2 Changed the VIDIFF maximum (peak-to-peak) to 1600 mV.
GTY and GTYP Transceiver Reference Clock Oscillator Selection Phase Noise Mask RINGPLL and LCPLL were mistakenly switched. The RINGPLL now has the 50 MHz offset frequency row.
2/29/2024 Version 1.6
General updates Updated Table 1 for production release of XCVE2202, XCVE2302, XCVE2602, XCVE2802 devices in speed grades -2MSE, -2MLE, -2MSI, -2MLI, -2LSE, -1MSE, -1MSI, -1MLI, -1LSE,  -1LSI, and -1LLI using the Vivado Design Suite 2023.2.1 v2.00 in Speed Grade Designations and Production Silicon and Software Status.

This includes updates to the following tables:

Absolute Maximum Ratings Revised the transceiver REFCLK_AC maximum input voltage from 1.200V to 1.350V.
Block RAM Switching Characteristics Changed maximum value of both TRCKO_DO and TRCKO_DO_REG in the -2LLI speed grade.
DDR4 and LPDDR4/4X Memory Interface Controller Removed the LPDDR4/4X pin efficient component interface limitation.
Table 2 Removed the rows, columns, and interface tiles connected to PL columns. See Versal Architecture and Product Data Sheet: Overview (DS950) for the most up to date information.
Table 2 Added the VICM specification. To support LVPECL clocks, changed the VIDIFF maximum (peak-to-peak) to 800 mV.
GTY and GTYP Transceiver User Clock Switching Characteristics Updated the -2H values.
11/09/2023 Version 1.5
General updates Updated for production release of XCVE1752 -2LLI speed grade. Updated Table 1 including production release of the XCVE1752 with speed grade -2LLI (VCCINT = 0.70V) using the Vivado Design Suite 2023.2 v2.04 in Speed Grade Designations and Production Silicon and Software Status.
Recommended Operating Conditions Updated Note 9 with PSIO operation information. Updated Note 10.
Available Speed Grades and Operating Voltages Updated Note 4.
Device Identification Updated the device ID for XCVE2202.
Package Parameter Guidelines Added more package values.
DDR4 and LPDDR4/4X Memory Interface Controller Clarified the values for LPDDR4/4X XPIO bank performance.
GTY and GTYP Transceiver Reference Clock Switching Characteristics Added Note 1.
GTY and GTYP Transceiver Digital Monitor Clock Added table.
9/11/2023 Version 1.4
General updates For XCVE2602 and XCVE2802, removed -3H speed grade and added -2HSI/-2LLI speed grades throughout data sheet.
Absolute Maximum Ratings Added Note 10.
Clocks and Reset Added FHSM0_REFCLK to Table 7.
GTY and GTYP Transceiver Electrical Compliance Clarified PCIe support for GTYP transceivers.
5/09/2023 Version 1.3
Absolute Maximum Ratings Updated VCC_SOC description.
Recommended Operating Conditions Updated VCC_SOC description.
DC Characteristics Over Recommended Operating Conditions Added IL specifications.
Speed Grade Designations Moved XCVE1752 in -2HSI to production.
Production Silicon and Software Status Moved XCVE1752 in -2HSI to production in Vivado Design Suite 2022.2.2 v2.02.
Device Identification Updated XCVE2602 and XCVE2802 IDCODEs.
Table 4 Added Notes 1, 2, and 3.
Table 5 Added Notes 2, 4, 6, 8, 10, and 12.
PS Gigabit Ethernet MAC Controller Interface Added Note 2 to FGEMTSUREFCLK.
Package Parameter Guidelines Corrected the XCVE2602 and XCVE2802 package to VSVH1760 and added values for XCVE2802.
AI Engine Switching Characteristics Updated the column values for VE2002 and VE2202.
GTY and GTYP Transceiver DC Input and Output Levels Removed the row for VCMOUTDC when remote RX is terminated to GND and added Note 2. Updated Note 3.
Integrated Block for MRMAC Added supported data rates for Versal AI Edge devices and updated table notes.
3/28/2023 Version 1.2
General updates Updated the Table 1 including production release of the XCVE1752 with speed grades

-2MSE, -2MLE, -2MSI, -2MLI, -1MSE, -1MSI, -1MLI (VCCINT = 0.80V) using the Vivado Design Suite 2022.2.1 v2.01 in Speed Grade Designations and Production Silicon and Software Status.

Available Speed Grades and Operating Voltages Updated -2LLI device code and added Note 5.
Updated VCC_CPM5 values because devices with CPM5 do not support the -2HSI or -2LLI speed grades.
Updated Notes 1, 2, and 3.
Speed Grade Designations Clarified that -2LLI for the VE1752 is in evaluation.
Device Identification Updated table.
PMC JTAG and SelectMAP Added Note 1 to FTCK.
12/05/2022 Version 1.1
General updates Updated the Table 1 including production release of the XCVE1752 with speed grades -2LSE, -2LLE, -2LLI, -1LSE, -1LSI, and -1LLI (VCCINT = 0.70V) using the Vivado Design Suite 2022.2 v2.00 in Speed Grade Designations and Production Silicon and Software Status.
DC Characteristics Over Recommended Operating Conditions Updated the ICC_BATT conditions and values.
Processing System Performance Characteristics Updated Table 1 and Table 2.
PMC Quad-SPI Controller Interface Updated the FQSPI_REFCLK maximum for Quad-SPI device clock frequency operating at ≤37.5 MHz (Loopback disabled) from 150 MHz to 300 MHz.
PMC SD/SDIO Controller Interface Added SD/SDIO interface default speed mode input setup and hold time minimums. Revised the SD/SDIO interface SDR12 mode input setup time minimum.
PMC eMMC Controller Interface Added eMMC interface standard mode input setup and hold time minimums.
Accelerator RAM Switching Characteristics Revised the -3 and -2 (VCC_PSLP = 0.88V) maximum accelerator RAM clock frequency.
Device Pin-to-Pin Output Parameter Guidelines Revised values for VE1752.
Device Pin-to-Pin Input Parameter Guidelines Revised values for VE1752.
Package Parameter Guidelines Revised values for VE1752.
GTY and GTYP Transceiver DC Input and Output Levels Revised VCMOUTDC and VCMOUTAC equations.
GTY and GTYP Transceiver Performance In Table 2, revised the GTYP maximum line rate and the LCPLL line rate range.
GTY and GTYP Transceiver User Clock Switching Characteristics Updated FTXIN and FRXIN values for some data width conditions.
Programmable Logic Integrated Block for PCIe Updated notes for support of PCI Express Gen4.
Table 4 Revised some of the -1 (VCCINT_CPM5 = 0.70V) overdrive values. Gen5x8 is not supported.
Table 5 Revised some of the overdrive mode frequencies. Gen5x8 is not supported.
Table 6 Revised some of the -1 (VCCINT = 0.70V) overdrive values. Gen5x8 is not supported.
Video Decoder Engines Performance Updated values and note.
5/02/2022 Version 1.0
Initial release. N/A