PS Gigabit Ethernet MAC Controller Interface

Versal AI Edge Series Data Sheet: DC and AC Switching Characteristics (DS958)
Document ID
DS958
Release Date
2024-09-24
Revision
1.9 English
Table 1. RGMII Interface
Symbol Description 1 Min Max Units
FGEMTXCLK RGMII_TX_CLK transmit clock frequency – 125 MHz
FGEMRXCLK RGMII_RX_CLK receive clock frequency – 125 MHz
FGEMREFCLK Gigabit Ethernet MAC (GEM) reference clock frequency – 125 MHz
FGEMTSUREFCLK 2 Gigabit Ethernet MAC time-stamp unit reference clock frequency – 250 MHz
TDCGEMTXCLK Transmit clock duty cycle 45 55 %
TGEMTXCKO TXD output clock to out time –0.5 0.5 ns
TGEMRXDCK RXD input setup time 0.8 – ns
TGEMRXCKD RXD input hold time 0.8 – ns
TMDIOCLK MDC output clock period 400 – ns
TMDIOCKL MDC Low time 160 – ns
TMDIOCKH MDC High time 160 – ns
TMDIODCK MDIO input data setup time 80 – ns
TMDIOCKD MDIO input data hold time 0.0 – ns
TMDIOCKO MDIO output data delay time –3.0 15.0 ns
  1. The test conditions are configured to the LVCMOS 3.3V I/O standard with a 12 mA drive strength, fast slew rate, and a 15 pF load.
  2. The APB interface (LPD_LSBUS_CLK) operating frequency must be greater than or equal to the GEM_TSU_CLK operating frequency.