PMC Quad-SPI Controller Interface

Versal AI Edge Series Data Sheet: DC and AC Switching Characteristics (DS958)
Document ID
DS958
Release Date
2024-11-22
Revision
1.10 English
Table 1. Quad-SPI Interface
Symbol Description 1, 2 Min Max Units
Quad-SPI device clock frequency operating at >100 MHz up to 150 MHz. Loopback enabled. 3
FQSPI_CLK Quad-SPI device clock frequency 100 150 MHz
FQSPI_REFCLK 4 Quad-SPI reference clock frequency 2 × FQSPI_CLK MHz
TQSPIDCK Setup time, all inputs 0.77 – ns
TQSPICKD Hold time, all inputs 1.0 – ns
TQSPICKO Clock to output delay, all outputs 2.9 4.5 ns
TQSPICSCLK 5 Chip select asserted to next clock edge 5.0 – ns
TQSPICLKCS Clock edge to chip select deasserted 5.0 – ns
TDCQSPICLK Quad-SPI clock duty cycle 45 55 %
Quad-SPI device clock frequency operating at >37.5 MHz up to 100 MHz. Loopback enabled. 3
FQSPI_CLK Quad-SPI device clock frequency 37.5 100 MHz
FQSPI_REFCLK 4 Quad-SPI reference clock frequency 2 × FQSPI_CLK MHz
TQSPIDCK Setup time, all inputs 2.0 – ns
TQSPICKD Hold time, all inputs 0.0 – ns
TQSPICKO Clock to output delay, all outputs 3.2 7.8 ns
TQSPICSCLK 5 Chip select asserted to next clock edge 5.0 – ns
TQSPICLKCS Clock edge to chip select deasserted 5.0 – ns
TDCQSPICLK Quad-SPI clock duty cycle 45 55 %
Quad-SPI device clock frequency operating at ≤37.5 MHz. Loopback disabled.
FQSPI_CLK Quad-SPI device clock frequency   37.5 MHz
FQSPI_REFCLK 4 Quad-SPI reference clock frequency   300 MHz
TQSPIDCK Setup time, all inputs 19.1 – ns
TQSPICKD Hold time, all inputs 0.0 – ns
TQSPICKO Clock to output delay, all outputs 5.2 21.5 ns
TQSPICSCLK Chip select asserted to next clock edge 9.0 – ns
TQSPICLKCS 5 Clock edge to chip select deasserted 9.0 – ns
TDCQSPICLK Quad-SPI clock duty cycle 45 55 %
  1. The test conditions are configured for the generic Quad-SPI interface with a 12 mA drive strength, fast slew rate, and load conditions (15 pF/30 pF for a Quad-SPI device clock frequency up to 100 MHz and 15 pF for a Quad-SPI device clock frequency > 100 MHz), tested at 3.3V and 1.8V.
  2. 30 pF loads are for QSPI dual-stacked or QSPI dual-parallel modes.
  3. When the Quad-SPI device clock frequency is >37.5 MHz, the Quad-SPI loopback clock output (QSPI_LPBK_CLK) must be enabled in the control, interface, and processing system (CIPS), and the associated MIO[6] pin must be left unconnected on the board.
  4. The Quad-SPI reference clock frequency must be 2x the Quad-SPI device clock frequency when it is >37.5 MHz.
  5. TQSPICSCLK is only valid when two reference clock cycles are programmed between the chip select and clock.