PMC JTAG and SelectMAP

Versal AI Edge Series Data Sheet: DC and AC Switching Characteristics (DS958)
Document ID
DS958
Release Date
2024-11-22
Revision
1.10 English
Table 1. JTAG/Boundary-Scan Port Switching Characteristics
Symbol Description Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.725V (L) 0.70V (L)
-2 -2 -1 -2LLI -1 -2 -1
FTCK 1 JTAG clock frequency 70 70 70 60 60 60 60 MHz, Max
TTCKL 1 TCK Low pulse time 5.5 5.5 5.5 6.0 6.0 6.0 6.0 ns, Min
TTCKH TCK High pulse time 2.0 2.0 2.0 2.0 2.0 2.0 2.0 ns, Min
TTAPTCK/TTCKTAP TMS and TDI setup and hold 3.0/2.0 3.0/2.0 3.0/2.0 3.0/2.0 3.0/2.0 3.0/2.0 3.0/2.0 ns, Min
TTCKTDO TCK falling edge to TDO output 5.5 5.5 5.5 6.0 6.0 6.0 6.0 ns, Max
  1. When using AC-JTAG, the maximum FTCK frequency is 40 MHz and the minimum TTCKL low pulse time is 7 ns.
Table 2. SelectMap Interface Switching Characteristics
Symbol Description Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.725V (L) 0.70V (L)
-2 -2 -1 -2LLI -1 -2 -1
FSMAPCLK SelectMap clock frequency, write 200 200 200 200 200 200 200 MHz, Max
SelectMap clock frequency, read 120 120 120 120 120 120 120 MHz, Max
TSMAPCLKL SelectMAP clock Low time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns, Min
TSMAPCLKH SelectMAP clock High time 2.5 2.5 2.5 2.5 2.5 2.5 2.5 ns, Min
TSMAPDCLK/SMAPCLKD SelectMAP data (SMAP_IO[31:0]) setup and hold 3.0/0.0 3.0/0.0 3.0/0.0 4.5/0.0 4.5/0.0 4.5/0.0 4.5/0.0 ns, Min
TSMAPCSCLK/SMAPCLKCS SelectMAP chip select (SMAP_CS_b) setup and hold 3.0/0.0 3.0/0.0 3.0/0.0 4.0/0.0 4.0/0.0 4.0/0.0 4.0/0.0 ns, Min
TSMAPRWCLK/SMAPCLKRW SelectMAP read write (SMAP_RDWR_b) setup and hold 3.0/0.0 3.0/0.0 3.0/0.0 4.0/0.0 4.0/0.0 4.0/0.0 4.0/0.0 ns, Min
TSMAPCLKO SelectMAP clock to data output 13.0 13.0 13.0 13.0 13.0 13.0 13.0 ns, Max
CSMAPBUSYCS SelectMAP busy assertion to chip select deassertion 24 24 24 24 24 24 24 clock cycles, Max