MMCM Switching Characteristics

Versal AI Edge Series Data Sheet: DC and AC Switching Characteristics (DS958)
Document ID
DS958
Release Date
2024-11-22
Revision
1.10 English
Table 1. MMCM Specification
Symbol Description Performance as a Function of Speed Grade and Operating Voltage (VCC_RAM) Units
0.88V (H) 0.80V (M) 0.80V (L) 1
-2 -2 -1 -2 -1
FINMAX_MMCM Maximum input clock frequency 2 1150 1070 984 800 680 MHz
FINMIN_MMCM Minimum input clock frequency 10 10 10 10 10 MHz
FINJITTER_MMCM Maximum input clock period jitter 3 < 20% of clock input period or 1 ns Max
FINDUTY_MMCM Input duty cycle range: 10–49 MHz 25–75 %
Input duty cycle range: 50–199 MHz 30–70 %
Input duty cycle range: 200–399 MHz 35–65 %
Input duty cycle range: 400–499 MHz 40–60 %
Input duty cycle range: >500 MHz 45–55 %
FMAX_PSCLK_MMCM Maximum dynamic phase shift clock frequency 500 500 450 500 450 MHz
FMIN_PSCLK_MMCM Minimum dynamic phase shift clock frequency 0.01 0.01 0.01 0.01 0.01 MHz
FVCOMAX_MMCM Maximum MMCM VCO frequency 4320 4320 4320 4320 4320 MHz
FVCOMIN_MMCM Minimum MMCM VCO frequency 2160 2160 2160 2160 2160 MHz
FBANDWIDTH_MMCM Low MMCM bandwidth at typical 4 1.00 1.00 1.00 1.00 1.00 MHz
High MMCM bandwidth at typical 4 4.00 4.00 4.00 4.00 4.00 MHz
TSTATPHAOFFSET_MMCM Static phase offset of the MMCM outputs 5 0.12 0.12 0.12 0.12 0.12 ns
TOUTJITTER_MMCM MMCM output jitter Note 6
TOUTDUTY_MMCM MMCM output clock duty cycle precision 7 0.20 0.20 0.20 0.20 0.20 ns
TLOCKMAX_MMCM MMCM maximum lock time (non deskew mode) 100 100 100 100 100 µs
TLOCKDESKEWMAX_MMCM MMCM maximum lock time in deskew mode Note 8
FOUTMAX_MMCM MMCM maximum output clock frequency 2 1150 1070 984 800 680 MHz
FOUTMIN_MMCM MMCM minimum output clock frequency 5 5 5 5 5 MHz
TEXTFDVAR_MMCM External clock feedback variation < 20% of clock input period or 1 ns Max
TPWRDWNMINPULSE_MMCM Minimum power-down pulse width 5.00 5.00 5.00 5.00 5.00 ns
FPFDMAX_MMCM Maximum frequency at the phase frequency detector with bandwidth set to High or optimized 500 500 450 500 450 MHz
Maximum frequency at the phase frequency detector with bandwidth set to Low 500 500 450 500 450 MHz
FPFDMIN_MMCM Minimum frequency at the phase frequency detector 10 10 10 10 10 MHz
TFBDELAY_MMCM Maximum delay in the feedback path 9 3 ns Max or one clock cycle
TDESKEWTAPDELAY_MMCM Nominal tap-delay of the programmable delay in the PD based deskew scheme Note 10
  1. The MMCM is powered by the VCC_RAM supply that operates at 0.80V in low (L) voltage operation, see Table 1 .
  2. The maximum input and output clock frequencies are limited by the global clock buffers. See Table 1.
  3. CLKIN jitter also applies to CLKIN_DESKEW and CLKFB_DESKEW in digital compensation. CLKFBIN applies only to analog compensation. This parameter is in regards to the functionality of the MMCM. Input jitter above ~1 MHz is reduced by the filtering properties of the MMCM. The magnitude of the reduction is found in the Vivado timing report.
  4. The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.
  5. The static offset is measured between any MMCM outputs with identical phase.
  6. Values for this parameter are available in the Vivado timing summary as part of the clock uncertainty equation.
  7. Includes global clock buffer.
  8. The maximum lock time in deskew mode is given by the following formula: Lock time in deskew mode in ms = (0.208 x (VCO_frequency in MHz) / (CLKIN_DESKEW_frequency in MHz)2) + 0.1.
  9. The parameter only applies to analog compensation.
  10. The value for this parameter is included in compensation delay calculations.