Device Pin-to-Pin Output Parameter Guidelines

Versal AI Edge Series Data Sheet: DC and AC Switching Characteristics (DS958)

Document ID
DS958
Release Date
2024-04-30
Revision
1.7 English

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.

Table 1. Global Clock Input to Output Delay With MMCM (Internal Mode)
Symbol Description 1, 2 Device Performance as a Function of Speed Grade and Operating Voltage (VCCINT) Units
0.88V (H) 0.80V (M) 0.70V (L)
-2 -2 -1 -2LLI -2LSE

-2LLE

-1
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM
TICKOFMMCM Global clock input and output flip-flop with MMCM XCVE1752 6.97 7.52 7.98 8.21 8.21 8.81 ns
XCVE2002 4.30 4.67 4.96 4.68 4.68 4.97 ns
XCVE2102 4.30 4.67 4.96 4.68 4.68 4.97 ns
XCVE2202 6.08 6.60 7.06 7.27 7.33 7.94 ns
XCVE2302 6.08 6.60 7.06 7.27 7.33 7.94 ns
XCVE2602 6.73 7.31 7.78 7.93 8.00 8.61 ns
XCVE2802 6.73 7.31 7.78 7.93 8.00 8.61 ns
  1. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
  2. MMCM output jitter is already included in the timing calculation.