Device Pin-to-Pin Output Parameter Guidelines

Versal AI Edge Series Data Sheet: DC and AC Switching Characteristics (DS958)

Document ID

DS958

Release Date

2024-09-24

Revision

1.9 English

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.

Table 1. Global Clock Input to Output Delay With MMCM (Internal Mode)
Symbol	Description^{1, 2}	Device	Performance as a Function of Speed Grade and Operating Voltage (V_CCINT)								Units
			0.88V (H)	0.80V (M)			0.725V (L)		0.70V (L)
			-2	-2	-1	-1MM	-2LLI	-1	-2LSE -2LLE	-1
SSTL15 Global Clock Input to Output Delay using Output Flip-Flop, Fast Slew Rate, with MMCM
T_ICKOFMMCM	Global clock input and output flip-flop with MMCM	XCVE1752	6.97	7.52	7.98	N/A	8.21	N/A	8.21	8.81	ns
		XCVE2002	4.30	4.67	4.96	N/A	4.68	N/A	4.68	4.97	ns
		XCVE2102	4.30	4.67	4.96	N/A	4.68	N/A	4.68	4.97	ns
		XCVE2202	6.08	6.60	7.06	N/A	7.27	N/A	7.33	7.94	ns
		XCVE2302	6.08	6.60	7.06	N/A	7.27	N/A	7.33	7.94	ns
		XCVE2602	6.73	7.31	7.78	N/A	8.00	N/A	8.00	8.61	ns
		XCVE2802	6.73	7.31	7.78	N/A	8.00	N/A	8.00	8.61	ns
		XAVE1752	N/A	N/A	N/A	N/A	N/A	8.87	N/A	N/A	ns
		XQVE2102	N/A	4.67	4.96	4.97	N/A	N/A	N/A	4.97	ns
		XQVE2302	N/A	6.60	7.06	7.11	N/A	N/A	N/A	7.94	ns
This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net. MMCM output jitter is already included in the timing calculation.