DC Characteristics Over Recommended Operating Conditions

Versal AI Edge Series Data Sheet: DC and AC Switching Characteristics (DS958)

Document ID
DS958
Release Date
2024-02-29
Revision
1.6 English
Table 1. DC Characteristics Over Recommended Operating Conditions
Symbol Description Min Typ 1 Max Units
CIN 2 HDIO and PSIO die input capacitance at the pad 3.50 pF
XPIO die input capacitance at the pad 1.75 pF
IL

HDIO, XPIO, and PSIO input or output leakage current per pin (sample-tested)

15 µA
IRPU Pad pull-up (when selected) at VIN = 0V, VCCO = 3.3V 60 200 µA
Pad pull-up (when selected) at VIN = 0V, VCCO = 2.5V 50 169 µA
Pad pull-up (when selected) at VIN = 0V, VCCO = 1.8V 29 120 µA
Pad pull-up (when selected) at VIN = 0V, VCCO = 1.5V 30 120 µA
Pad pull-up (when selected) at VIN = 0V, VCCO = 1.2V 10 100 µA
IRPD Pad pull-down (when selected) at VIN = 3.3V 60 200 µA
Pad pull-down (when selected) at VIN = 1.8V 29 120 µA
ICC_FUSE VCC_FUSE supply current during eFUSE programming 165 mA
Battery Supply Current
ICC_BATT 3, 4 Battery supply current at VCC_BATT = 1.20V, RTC disabled 160 nA
Battery supply current at VCC_BATT = 1.50V, RTC disabled 320 nA
Battery supply current at VCC_BATT = 1.20V, RTC enabled 1360 nA
Battery supply current at VCC_BATT = 1.50V, RTC enabled 1930 nA
Calibrated programmable on-die termination (DCI) in XPIO banks 5 (measured per JEDEC specification)
R 7 Thevenin equivalent resistance of programmable input termination where x = target impedance of 48, 60, 120, or 240 –20% 6 ODT = RTT_x +20% 6 Ω
Uncalibrated programmable on-die termination in HDIO banks (measured per JEDEC specification)
R 7 Thevenin equivalent resistance of programmable input termination to VCCO/2 where ODT = RTT_48 –50% 48 +50% Ω
Differential termination Programmable differential termination (TERM_100) for XPIO banks –35% 100 +35% Ω
  1. Typical values are specified at nominal voltage, 25°C.
  2. This measurement represents the die capacitance at the pad, not including the package.
  3. Maximum value specified for worst case process at 25°C.
  4. Battery-backed RAM (BBRAM) is always enabled and included in ICC_BATT .
  5. VR resistor tolerance is (240Ω ±1%).
  6. The tolerance limits are specified after calibration with stable voltage and temperature.
  7. On-die input termination resistance, for more information see the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).