SelectIO Levels for X5IO Banks - DS956

Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956)

Document ID
DS956
Release Date
2025-01-13
Revision
1.14 English
Table 1. SelectIO DC Input and Output Levels for X5IO Banks
I/O Standard 1, 2 , 3 VIL VIH VOL VOH IOL IOH
V, Min V, Max V, Min V, Max V, Max V, Min mA mA
HSTL_I_12 –0.100 50% VCCO – 0.080 50% VCCO + 0.080 VCCO 25% VCCO 75% VCCO 4.1 –4.1
HSUL_12 –0.100 50% VCCO – 0.130 50% VCCO + 0.130 VCCO 20% VCCO 80% VCCO 0.1 –0.1
LVCMOS10 –0.100 35% VCCO 65% VCCO VCCO 0.400 VCCO – 0.400 Note 4 Note 4
LVCMOS11 –0.100 35% VCCO 65% VCCO VCCO 0.400 VCCO – 0.400 Note 4 Note 4
LVCMOS12 –0.100 35% VCCO 65% VCCO VCCO 0.400 VCCO – 0.400 Note 4 Note 4
SSTL10 –0.100 50% VCCO – 0.130 50% VCCO + 0.130 VCCO VCCO/2 – 0.150 VCCO/2 + 0.150 6.0 –6.0
SSTL11 –0.100 50% VCCO – 0.130 50% VCCO + 0.130 VCCO VCCO/2 – 0.150 VCCO/2 + 0.150 7.0 –7.0
SSTL12 –0.100 50% VCCO – 0.100 50% VCCO + 0.100 VCCO VCCO/2 – 0.150 VCCO/2 + 0.150 8.0 –8.0
  1. Tested according to relevant specifications.
  2. Standards specified using the default I/O standard configuration. For details, see the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).
  3. POD10, POD11, and POD12 DC input and output levels are shown in Table 2, Table 6, and Table 7.
  4. Supported drive strengths of 2, 4, 6, or 8 mA in X5IO banks.
Table 2. DC Input Levels for Single-ended POD10, POD11, POD12, LVSTL05_10, LVSTL06_12, and LVSTL_11 I/O Standards
I/O Standard 1, 3 VIL VIH
V, Min V, Max V, Min V, Max
POD10 –0.100 70% VCCO – 0.068 70% VCCO + 0.068 VCCO
POD11 –0.100 70% VCCO – 0.068 70% VCCO + 0.068 VCCO
POD12 –0.100 70% VCCO – 0.068 70% VCCO + 0.068 VCCO
LVSTL05_10 –0.100 VCCO/8 – 0.100 VCCO/8 + 0.100 VCCO
LVSTL06_12 –0.100 VCCO/8 – 0.100 VCCO/8 + 0.100 VCCO
LVSTL_11 –0.100 VCCO/6 – 0.100 VCCO/6 + 0.100 VCCO
  1. Tested according to relevant specifications.
  2. Standards specified using the default I/O standard configuration. For details, see the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).
Table 3. Differential SelectIO DC Input and Output Levels for MIPI_DPHY and MIPI_CPHY
I/O Standard VICM (V) 1 VID (V) 2 VILHS 3 VIHHS 3 VOCM (V) 4 VOD (V) 5
Min Typ Max Min Typ Max Min Max Min Typ Max Min Typ Max
MIPI_DPHY for operation <1.5 GB/s 6 0.070 0.330 0.070 –0.040 0.460 0.150 0.200 0.250 0.140 0.200 0.270
MIPI_DPHY for operation at >1.5G GB/s 6 0.070 0.330 0.040 –0.040 0.460 0.150 0.200 0.250 0.140 0.200 0.270
MIPI_CPHY 0.095 0.390 0.040 –0.040 0.535 0.175 0.225–0.250 0.310 0.090 7 0.300 8
  1. VICM is the input common mode voltage.
  2. VID is the input differential voltage (Q – Q).
  3. VIHHS and VILHS are the single-ended input high and low voltages, respectively.
  4. VOCM is the output common mode voltage.
  5. VOD is the output differential voltage (Q – Q).
  6. High-speed option for MIPI_DPHY. The VID maximum is aligned with the standard’s specification. A higher VID is acceptable as long as the VIN specification is also met.
  7. Minimum for VOD weak.
  8. Maximum for VOD strong.
Table 4. Complementary Differential SelectIO DC Input and Output Levels for X5IO Banks
I/O Standard 1 VICM (V) 2 VID (V) 3 VOL (V) 4 VOH (V) 5 IOL IOH
Min Typ Max Min Max Max Min mA mA
DIFF_HSTL_I_12 0.400 x VCCO VCCO/2 0.600 x VCCO 0.100 0.250 x VCCO 0.750 x VCCO 4.1 –4.1
DIFF_HSUL_12 (VCCO/2) – 0.120 VCCO/2 (VCCO/2) + 0.120 0.100 20% VCCO 80% VCCO 0.1 –0.1
DIFF_SSTL10 (VCCO/2) – 0.150 VCCO/2 (VCCO/2) + 0.150 0.100 (VCCO/2) – 0.150 (VCCO/2) + 0.150 6.0 –6.0
DIFF_SSTL11 (VCCO/2) – 0.150 VCCO/2 (VCCO/2) + 0.150 0.100 (VCCO/2) – 0.150 (VCCO/2) + 0.150 7.0 –7.0
DIFF_SSTL12 (VCCO/2) – 0.150 VCCO/2 (VCCO/2) + 0.150 0.100 (VCCO/2) – 0.150 (VCCO/2) + 0.150 8.0 –8.0
  1. DIFF_POD10, DIFF_POD11, and DIFF_POD12 X5IO bank specifications are shown in Table 5, Table 6, and Table 7.
  2. VICM is the input common mode voltage.
  3. VID is the input differential voltage.
  4. VOL is the single-ended low-output voltage.
  5. VOH is the single-ended high-output voltage.
Table 5. DC Input Levels for Differential POD10, POD11, POD12, LVSTL05_10, LVSTL06_12, and LVSTL_11 I/O Standards
I/O Standard 1, 2 VICM (V) VID (V)
Min Typ Max Min Max
DIFF_POD10 0.630 0.700 0.770 0.140
DIFF_POD11 0.693 0.77 0.847 0.150
DIFF_POD12 0.756 0.840 0.924 0.160
DIFF_LVSTL05_10 0.113 0.125 0.138 0.150
DIFF_LVSTL06_12 0.143 0.150 0.157 0.140
DIFF_LVSTL_11 0.174 0.183 0.193 0.140
  1. Tested according to relevant specifications.
  2. Standards specified using the default I/O standard configuration. For details, see the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).
Table 6. DC Output Levels for Single-ended and Differential POD10, POD11, POD12, LVSTL05_10, LVSTL06_12, and LVSTL_11 I/O Standards
I/O Standard Symbol Description 1, 2, 3 VOUT Min Typ Max Units
POD10, POD11, POD12 ROL Pull-down resistance VOM_DC (as described in Table 7) 32 40 48 Ω
ROH Pull-up resistance VOM_DC (as described in Table 7) 32 40 48 Ω
LVSTL05_10 ROL Pull-down resistance VOCM_DC_LOW 32 40 48 Ω
ROH Pull-up resistance VOCM_DC_HIGH 32 40 48 Ω
LVSTL06_12 ROL Pull-down resistance VOCM_DC_LOW 32 40 48 Ω
ROH Pull-up resistance VOCM_DC_HIGH 32 40 48 Ω
LVSTL_11 ROL Pull-down resistance VOM_DC (as described in Table 7) 32 40 48 Ω
ROH Pull-up resistance VOM_DC (as described in Table 7) 32 40 48 Ω
  1. Tested according to relevant specifications.
  2. The tolerance limits are specified after calibration with stable voltage and temperature.
  3. Standards specified using the default I/O standard configuration. For details, see the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010).
Table 7. Definitions for DC Output Levels for Single-ended and Differential POD10, POD 11, POD12, LVSTL05_10, LVSTL06_12, and LVSTL_11 I/O Standards
I/O Standard Symbol Description All Speed Grades Units
POD10, POD11, POD12 VOM_DC DC output mid measurement level (for IV curve linearity) 0.8 x VCCO V
LVSTL_11 VOM_DC DC output mid measurement level (for IV curve linearity) VCCO/3 V
LVSTL05_10 VOM_DC DC output mid measurement level (for IV curve linearity) VCCO/4 V
LVSTL06_12 VOCM_DC DC output mid measurement level (for IV curve linearity) VCCO/4 V