PMC SD/SDIO Controller Interface

PMC SD/SDIO Controller Interface - DS956

Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956)

Document ID

DS956

Release Date

2025-03-14

Revision

1.15 English

Table 1. SD/SDIO Interface
Symbol	Description¹	Min	Max	Units
F_{SD_REFCLK}	SD reference clock frequency	–	200	MHz
F_{SDDLL_REFCLK}	SD DLL reference clock frequency	–	1200	MHz
SD/SDIO Interface Default Speed Mode
F_{SDS_CLK} ²	SD standard device clock frequency	–	20	MHz
F_{SDID_CLK}	Clock frequency in identification mode	–	400	kHz
T_{SDDC_CLK}	SD standard device clock duty cycle	45	55	%
T_SDCKO	Clock to output delay, all outputs	–2.0	4.5	ns
T_SDDCK	Input setup time, all inputs	2.0	–	ns
T_SDCKD	Input hold time, all inputs	2.0	–	ns
SD/SDIO Interface High-speed Mode
F_{SDHS_CLK}	SD high-speed device clock frequency	25	50	MHz
T_{SDHSDC_CLK}	SD high-speed device clock duty cycle	45	55	%
T_SDHSCKO	Clock to output delay, all outputs	2.2	13.8	ns
T_SDHSDIVW	Input valid data window	0.4	–	UI
SD/SDIO Interface SDR12 Mode
F_{SDSDR12_CLK} ²	SD SDR12 device clock frequency	–	25	MHz
T_{DCSDSDR12_CLK}	SD SDR12 device clock duty cycle	30	70	%
T_SDSDR12CKO	Clock to output delay, all outputs	1.0	36.8	ns
T_SDSDR12DCK	Input setup time, all inputs	10.0	–	ns
T_SDSDR12CKD	Input hold time, all inputs	1.5	–	ns
SD/SDIO Interface SDR25/SDR50 Mode
F_{SDSDR_CLK}	SDR25 device clock frequency	25	50	MHz
F_{SDSDR_CLK}	SDR50 device clock frequency	25	100	MHz
T_{SDSDRDC_CLK}	SD SDR50/SDR25 device clock duty cycle	30	70	%
T_SDSDRCKO	Clock to output delay, all outputs	1.0	6.8	ns
T_SDDDRCKD	Input valid data window	0.4	–	UI
SD/SDIO Interface SDR104 Mode
F_{SDSDR104_CLK}	SDR104 device clock frequency	25	200	MHz
T_{DCSDSDR104_CLK}	SD SDR104 device clock duty cycle	30	70	%
T_SDSDR104CKO	Clock to output delay, all outputs	1.0	3.2	ns
T_SDSDR104CKD	Input valid data window	0.5	–	UI
SD/SDIO Interface DDR50 Mode
F_{SDDDR_CLK}	SD DDR50 device clock frequency	25	50	MHz
T_{DCSDDDR_CLK}	SD DDR50 device clock duty cycle	45	55	%
T_SDDDRCKO	Clock to output delay, data	1.0	6.8	ns
T_SDDDRDCK	Input valid data window	0.5	–	UI
T_SDDDRCKD	Input setup time, command	4.7	–	ns
T_SDDDRIDCLK	Input hold time, command	1.5	–	ns
T_SDDDRCLK	Clock to output delay, command	1.0	13.8	ns
The test condition settings for SD/SDIO modes are: 12 mA drive strength, fast slew rate, and a 15 pF load. The OTAP delay (OTAP_DLY[5:0] ) test condition settings are: SD high-speed mode = `0x04`, SD SDR25/50 mode = `0x03`, SD SDR104 mode = `0x02`, and SD DDR50 mode = `0x03`. EMIO is supported in SD default speed mode and SDR12 mode.