LVDS DC Specifications (LVDS15) - DS956

Versal Prime Series Data Sheet: DC and AC Switching Characteristics (DS956)

Document ID: DS956
Release Date: 2025-03-14
Revision: 1.15 English

The LVDS15 standard is available in the XPIO banks. See the Versal Adaptive SoC SelectIO Resources Architecture Manual (AM010) for more information.

Table 1. LVDS15 DC Specifications
Symbol	DC Parameter	Conditions	Min	Typ	Max	Units
V_CCO ¹	Supply voltage		1.425	1.500	1.575	V
V_ODIFF ²	Differential output voltage: (Q – Q), Q = High (Q – Q), Q = High	R_T = 100Ω across Q and Q signals	247	350	454	mV
V_OCM ²	Output common-mode voltage	R_T = 100Ω across Q and Q signals	1.000	1.20	1.320	V
V_IDIFF ³	Differential input voltage: (Q – Q), Q = High (Q – Q), Q = High		100	350	600³	mV
V_{ICM_DC} ⁴	Input common-mode voltage (DC coupling)		0.300	1.200	1.320	V
V_{ICM_AC} ⁵	Input common-mode voltage (AC coupling)		200	–	330	mV
In XPIO banks, when LVDS15 is used with input-only functionality, it can be placed in a bank where the V_CCO levels are different from the specified level only if internal differential termination is not used. In this scenario, V_CCO must be chosen to ensure the input pin voltage levels do not violate the Recommended Operating Condition (Table 1) specification for the V_IN I/O pin voltage. V_OCM and V_ODIFF values are for LVDS_PRE_EMPHASIS = FALSE. Maximum V_IDIFF value is specified for the maximum V_ICM specification. With a lower V_ICM, a higher V_DIFF is tolerated only when the recommended operating conditions and overshoot/undershoot V_IN specifications are maintained. Input common mode voltage for DC coupled configurations. EQUALIZATION = EQ_NONE (Default). AC coupling with external bias and external differential termination with EQUALIZATION settings enabled. EQUALIZATION = EQ_LEVEL0, EQ_LEVEL1, EQ_LEVEL2, EQ_LEVEL3, or EQ_LEVEL4, any setting except EQ_NONE.