The following table provides the maximum data rates for applicable memory standards using the Versal Prime device memory PHY. Refer to the Programmable Network on Chip and Integrated DDR5/ LPDDR5 Memory Controller (PG406) for the complete list of memory interface standards supported and detailed specifications. The final performance of the memory interface is determined through a complete design implemented in the Vivado Design Suite, following guidelines in the Versal Adaptive SoC PCB Design User Guide (UG863), electrical analysis, and characterization of the system.
Memory Standard | DRAM Type | DIMM Slots | Performance as a Function of Speed Grade and Operating Voltage (VCC_SOC) | Units | ||||
---|---|---|---|---|---|---|---|---|
0.88V (H) | 0.80V (M) | 0.80V (L) 1 | ||||||
-2 | -2 | -1 | -2 | -1 | ||||
DDR5 | Single rank component | 5600 | 5600 | 5600 | 5600 | 5600 | Mb/s | |
1 rank DIMM 2 | 1 | 5600 | 5600 | 5600 | 5600 | 5600 | Mb/s | |
2 rank DIMM 2 | 1 | 5200 | 5200 | 5200 | 5200 | 5200 | Mb/s | |
1 rank RDIMM | 2 | 5600 | 5600 | 5600 | 5600 | 5600 | Mb/s | |
2 rank RDIMM | 2 | 5200 | 5200 | 5200 | 5200 | 5200 | Mb/s | |
LPDDR5 | Single rank component for VM2152 | 6400 | 6400 | 6400 | 6400 | 6400 | Mb/s | |
Single rank component for all other devices | 6400 | 6400 | 5600 | 6400 | 5600 | Mb/s | ||
Dual rank component for VM2152 | 6000 | 6000 | 6000 | 6000 | 6000 | Mb/s | ||
Dual rank component | 6000 | 6000 | 5200 | 6000 | 5200 | Mb/s | ||
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