Radiation Tolerant Versal AI Core Series Data Sheet (DS946)

Document ID: DS946
Release Date: 2023-03-28
Revision: 1.0 English

General Description
Summary of Radiation Parameters
Weibull Fit Parameters
Single Event Latch-up Results
Key Ruggedized Package Features
Summary of Features
Architecture
Compute and Acceleration
Platform Management
Connectivity
XQRVC1902-1MSBVSRA2197 Features
Device Layout (Architecture and Interconnect)
NoC
Platform Management Controller
Boot and Configuration
System Monitoring
Device Integrity and Debug
External Flash Memory Interfaces
Boot Modes
Compute and Acceleration Engines
AI Engine Array
Processing System
Application Processing Unit (APU)
Real-Time Processing Unit (RPU)
Connectivity Peripherals
Configurable Logic Block (CLB)
Internal Memory
On-Chip Memory (OCM)
Block RAM
UltraRAM
Digital Signal Processing (DSP)
Connectivity
GTY Transceivers
Integrated Block for PCI Express
Multirate Ethernet MAC
I/O
Clocking
Processing System Clocking
PL Clocking
Clock Management
Memory Controllers
DC Characteristics
Absolute Maximum Ratings
Recommended Operating Conditions
Available Speed Grades and Operating Voltages
DC Characteristics Over Recommended Operating Conditions
VIN Maximum Allowed AC Voltage Overshoot and Undershoot
DC Input and Output Levels
PSIO Levels
SelectIO Levels
LVDS DC Specifications (LVDS15)
Power Supply Requirements
AC Switching Characteristics
Testing of AC Switching Characteristics
Speed Grade Designations
Production Silicon and Software Status
Device Identification
Processing System Performance Characteristics
PS and PMC Switching Characteristics
Clocks and Reset
PMC JTAG and SelectMAP
PS and PMC Interface Specifications
PMC Quad-SPI Controller Interface
PMC Octal-SPI Controller Interface
PS SPI Controller Interface
PS USB Controller Interface
PS Gigabit Ethernet MAC Controller Interface
PMC SD/SDIO Controller Interface
PMC eMMC Controller Interface
PS and PMC I2C Controller Interface
PS CAN FD Controller Interface
PS UART Controller Interface
PS General Purpose I/O Interface
PS Trace Interface
PS Triple-timer Counter Interface
PS System Watchdog Timer Interface
PMC System Monitor Specifications
Network on Chip Switching Characteristics
Programmable Logic Performance Characteristics
Programmable Logic Switching Characteristics
Block RAM Switching Characteristics
UltraRAM Switching Characteristics
Input/Output Delay Switching Characteristics
DSP58 Switching Characteristics
Clock Buffers and Networks
MMCM Switching Characteristics
DPLL Switching Characteristics
XPLL Switching Characteristics
Device Pin-to-Pin Output Parameter Guidelines
Device Pin-to-Pin Input Parameter Guidelines
Package Parameter Guidelines
Memory Interface Controller
AI Engine Switching Characteristics
GTY Transceiver Specifications
GTY Transceiver DC Input and Output Levels
GTY Transceiver Switching Characteristics
GTY Transceiver Performance
GTY Transceiver Configuration Interface Port Switching Characteristics
GTY Transceiver Reference Clock Switching Characteristics
GTY Transceiver Reference Clock Oscillator Selection Phase Noise Mask
GTY Transceiver PLL/Lock Time Adaptation
GTY Transceiver User Clock Switching Characteristics
GTY Transceiver Transmitter and Receiver Switching Characteristics
GTY Transceiver Electrical Compliance
Integrated Block for MRMAC
Programmable Logic Integrated Block for PCIe
Integrated Blocks for PCIe with DMA and Cache Coherent Interconnect (CPM)
VSRA2197 Package for the XQRVC1902 Device Specifications
Pin Definitions
SelectIO Pin Definitions
Power Pin Definitions
PMCMIO, LPDMIO, PMCDIO Pin Definitions
GTY Transceiver Quad Pin Definitions
SYSMON Pin Definitions
XQRVC1902 Bank Diagram
ASCII Package File
VSRA2197—XQRVC1902 Pin Map
VSRA2197 Mechanical Drawing
Daisy Chain Package
Daisy Chain Netlist
Package Marking
Packing and Shipping
Soldering Guidelines
Sn/Pb Reflow Soldering
Peak Package Reflow Temperatures
Post Reflow/Cleaning/Washing
Strain Gauge Measurement
Solder Paste
Component Placement
Component Pick-up Tool Consideration
Recommended PCB Design Rules for BGA
Stencil
Edge Bonding Guidelines
Edge Bonding Implementation
Edge Bond Removal
Conformal Coating
Thermal Specifications
Support for Thermal Models
Thermal Management Strategy
Flip-Chip Packages
System Level Heat Sink Solutions
Thermal Interface Material
Types of TIM
Guidelines for Thermal Interface Materials
Heat Sink Removal
Measurement Debug
Mechanical and Thermal Design Guidelines for Lidless Flip-chip Packages
Lidless Flip-Chip Packages
Ordering Information
Revision History
Please Read: Important Legal Notices

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