GTH Transceiver Switching Characteristics

Consult the UltraScale Architecture GTH Transceivers User Guide (UG576) for further information.

Table 1. GTH Transceiver Performance
Symbol	Description	Output Divider	Speed Grade and V_CCINT Operating Voltages						Units
			0.85V				0.72V
			-2		-1		-1
F_GTHMAX	GTH maximum line rate		16.375¹		12.5		11.88²		Gb/s
F_GTHMIN	GTH minimum line rate		0.5		0.5		0.5		Gb/s
			Min	Max	Min	Max	Min	Max
F_GTHCRANGE	CPLL line rate range³	1	4	12.5	4	8.5	4	8.5	Gb/s
		2	2	6.25	2	4.25	2	4.25	Gb/s
		4	1	3.125	1	2.125	1	2.125	Gb/s
		8	0.5	1.5625	0.5	1.0625	0.5	1.0625	Gb/s
		16	N/A						Gb/s
			Min	Max	Min	Max	Min	Max
F_GTHQRANGE1	QPLL0 line rate range⁴	1	9.8	16.375	9.8	12.5	9.8	11.88²	Gb/s
		2	4.9	8.1875	4.9	8.15	4.9	8.15	Gb/s
		4	2.45	4.0938	2.45	4.075	2.45	4.075	Gb/s
		8	1.225	2.0469	1.225	2.0375	1.225	2.0375	Gb/s
		16	0.6125	1.0234	0.6125	1.0188	0.6125	1.0188	Gb/s
			Min	Max	Min	Max	Min	Max
F_GTHQRANGE2	QPLL1 line rate range⁵	1	8.0	13.0	8.0	12.5	8.0	11.88²	Gb/s
		2	4.0	6.5	4.0	6.5	4.0	6.5	Gb/s
		4	2.0	3.25	2.0	3.25	2.0	3.25	Gb/s
		8	1.0	1.625	1.0	1.625	1.0	1.625	Gb/s
		16	0.5	0.8125	0.5	0.8125	0.5	0.8125	Gb/s
			Min	Max	Min	Max	Min	Max
F_CPLLRANGE	CPLL frequency range		2	6.25	2	4.25	2	4.25	GHz
F_QPLL0RANGE	QPLL0 frequency range		9.8	16.375	9.8	16.375	9.8	16.375	GHz
F_QPLL1RANGE	QPLL1 frequency range		8	13	8	13	8	13	GHz
GTH transceiver line rates in the FCVA289, SFVB784, SBVC484, and UBVA368 packages support data rates up to 12.5 Gb/s. Vivado Design Suite 2023.1 or later is required for XCAU10P and XCAU15P designs in the -1L speed grade and V_CCINT = 0.72V operating voltage with GTH line rates > 10.3125 Gb/s. The values listed are the rounded results of the calculated equation (2 × CPLL_Frequency)/Output_Divider. The values listed are the rounded results of the calculated equation (QPLL0_Frequency)/Output_Divider. The values listed are the rounded results of the calculated equation (QPLL1_Frequency)/Output_Divider.

Table 2. GTH Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Symbol	Description	All Speed Grades	Units
F_GTHDRPCLK	GTHDRPCLK maximum frequency	250	MHz

Table 3. GTH Transceiver Reference Clock Switching Characteristics
Symbol	Description	Conditions	All Speed Grades			Units
Symbol	Description	Conditions	Min	Typ	Max	Units
F_GCLK	Reference clock frequency range		60	–	820	MHz
T_RCLK	Reference clock rise time	20% – 80%	–	200	–	ps
T_FCLK	Reference clock fall time	80% – 20%	–	200	–	ps
T_DCREF	Reference clock duty cycle	Transceiver PLL only	40	50	60	%

Table 4. GTH Transceiver Reference Clock Oscillator Selection Phase Noise Mask
Symbol	Description	Offset Frequency	Min	Typ	Max	Units
QPLL_REFCLKMASK ^{1, 2}	QPLL0/QPLL1 reference clock select phase noise mask at REFCLK frequency = 312.5 MHz	10 kHz	–	–	–105	dBc/Hz
		100 kHz	–	–	–124
		1 MHz	–	–	–130
CPLL_REFCLKMASK ^{1, 2}	CPLL reference clock select phase noise mask at REFCLK frequency = 312.5 MHz	10 kHz	–	–	–105	dBc/Hz
		100 kHz	–	–	–124
		1 MHz	–	–	–130
		50 MHz	–	–	–140
For reference clock frequencies other than 312.5 MHz, adjust the phase-noise mask values by 20 × Log(N/312.5) where N is the new reference clock frequency in MHz. This reference clock phase-noise mask is superseded by any reference clock phase-noise mask that is specified in a supported protocol, e.g., PCIe.

Table 5. GTH Transceiver PLL/Lock Time Adaptation
Symbol	Description	Conditions	All Speed Grades			Units
Symbol	Description	Conditions	Min	Typ	Max	Units
T_LOCK	Initial PLL lock		–	–	1	ms
T_DLOCK	Clock recovery phase acquisition and adaptation time for decision feedback equalizer (DFE)	After the PLL is locked to the reference clock, this is the time it takes to lock the clock data recovery (CDR) to the data present at the input.	–	50,000	37 x 10⁶	UI
T_DLOCK	Clock recovery phase acquisition and adaptation time for low-power mode (LPM) when the DFE is disabled		–	50,000	2.3 x 10⁶	UI

Table 6. GTH Transceiver User Clock Switching Characteristics
Symbol	Description¹	Data Width Conditions (Bit)		Speed Grade and V_CCINT Operating Voltages			Units
		Data Width Conditions (Bit)		0.85V		0.72V
		Internal Logic	Interconnect Logic	-2²	-1^{3, 4}	-1⁴
F_TXOUTPMA	TXOUTCLK maximum frequency sourced from OUTCLKPMA			511.719	390.625	322.266	MHz
F_RXOUTPMA	RXOUTCLK maximum frequency sourced from OUTCLKPMA			511.719	390.625	322.266	MHz
F_TXOUTPROGDIV	TXOUTCLK maximum frequency sourced from TXPROGDIVCLK			511.719	511.719	511.719	MHz
F_RXOUTPROGDIV	RXOUTCLK maximum frequency sourced from RXPROGDIVCLK			511.719	511.719	511.719	MHz
F_TXIN	TXUSRCLK⁵ maximum frequency	16	16, 32	511.719	390.625	371.25	MHz
		32	32, 64	511.719	390.625	371.25	MHz
		20	20, 40	409.375	312.500	297	MHz
		40	40, 80	409.375	312.500	297	MHz
F_RXIN	RXUSRCLK⁵ maximum frequency	16	16, 32	511.719	390.625	371.25	MHz
		32	32, 64	511.719	390.625	371.25	MHz
		20	20, 40	409.375	312.500	297	MHz
		40	40, 80	409.375	312.500	297	MHz
F_TXIN2	TXUSRCLK2⁵ maximum frequency	16	16	511.719	390.625	371.25	MHz
		16	32	255.859	195.313	185.625	MHz
		32	32	511.719	390.625	371.25	MHz
		32	64	255.859	195.313	185.625	MHz
		20	20	409.375	312.500	297	MHz
		20	40	204.688	156.250	148.5	MHz
		40	40	409.375	312.500	297	MHz
		40	80	204.688	156.250	148.5	MHz
F_RXIN2	RXUSRCLK2⁵ maximum frequency	16	16	511.719	390.625	371.25	MHz
		16	32	255.859	195.313	185.625	MHz
		32	32	511.719	390.625	371.25	MHz
		32	64	255.859	195.313	185.625	MHz
		20	20	409.375	312.500	297	MHz
		20	40	204.688	156.250	148.5	MHz
		40	40	409.375	312.500	297	MHz
		40	80	204.688	156.250	148.5	MHz
Clocking must be implemented as described in UltraScale Architecture GTH Transceivers User Guide (UG576). For speed grades -2E and -2I, a 16-bit and 20-bit internal data path can only be used for line rates less than 8.1875 Gb/s. For speed grades -1E, -1I, and -1Q, a 16-bit and 20-bit internal data path can only be used for line rates less than 6.25 Gb/s. For speed grade -1LI, a 16-bit and 20-bit internal data path can only be used for line rates less than 6.25 Gb/s when V_CCINT = 0.85V or 5.15625 Gb/s when V_CCINT = 0.72V. When the gearbox is used, these maximums refer to the XCLK. For more information, see the UltraScale Architecture GTH Transceivers User Guide (UG576).

Table 7. GTH Transceiver Transmitter Switching Characteristics
Symbol	Description	Condition	Min	Typ	Max	Units
F_GTHTX	Serial data rate range		0.500	–	F_GTHMAX	Gb/s
T_RTX	TX rise time	20%–80%	–	21	–	ps
T_FTX	TX fall time	80%–20%	–	21	–	ps
T_LLSKEW	TX lane-to-lane skew¹		–	–	500.00	ps
T_J16.375	Total jitter^{2, 4}	16.375 Gb/s	–	–	0.28	UI
D_J16.375	Deterministic jitter^{2, 4}	16.375 Gb/s	–	–	0.17	UI
T_J15.0	Total jitter^{2, 4}	15.0 Gb/s	–	–	0.28	UI
D_J15.0	Deterministic jitter^{2, 4}	15.0 Gb/s	–	–	0.17	UI
T_J14.1	Total jitter^{2, 4}	14.1 Gb/s	–	–	0.28	UI
D_J14.1	Deterministic jitter^{2, 4}	14.1 Gb/s	–	–	0.17	UI
T_J14.1	Total jitter^{2, 4}	14.025 Gb/s	–	–	0.28	UI
D_J14.1	Deterministic jitter^{2, 4}	14.025 Gb/s	–	–	0.17	UI
T_J13.1	Total jitter^{2, 4}	13.1 Gb/s	–	–	0.28	UI
D_J13.1	Deterministic jitter^{2, 4}	13.1 Gb/s	–	–	0.17	UI
T_{J12.5_QPLL}	Total jitter^{2, 4}	12.5 Gb/s	–	–	0.28	UI
D_{J12.5_QPLL}	Deterministic jitter^{2, 4}	12.5 Gb/s	–	–	0.17	UI
T_{J12.5_CPLL}	Total jitter^{3, 4}	12.5 Gb/s	–	–	0.33	UI
D_{J12.5_CPLL}	Deterministic jitter^{3, 4}	12.5 Gb/s	–	–	0.17	UI
T_{J11.3_QPLL}	Total jitter^{2, 4}	11.3 Gb/s	–	–	0.28	UI
D_{J11.3_QPLL}	Deterministic jitter^{2, 4}	11.3 Gb/s	–	–	0.17	UI
T_{J10.3125_QPLL}	Total jitter^{2, 4}	10.3125 Gb/s	–	–	0.28	UI
D_{J10.3125_QPLL}	Deterministic jitter^{2, 4}	10.3125 Gb/s	–	–	0.17	UI
T_{J10.3125_CPLL}	Total jitter^{3, 4}	10.3125 Gb/s	–	–	0.33	UI
D_{J10.3125_CPLL}	Deterministic jitter^{3, 4}	10.3125 Gb/s	–	–	0.17	UI
T_{J9.953_QPLL}	Total jitter^{2, 4}	9.953 Gb/s	–	–	0.28	UI
D_{J9.953_QPLL}	Deterministic jitter^{2, 4}	9.953 Gb/s	–	–	0.17	UI
T_{J9.953_CPLL}	Total jitter^{3, 4}	9.953 Gb/s	–	–	0.33	UI
D_{J9.953_CPLL}	Deterministic jitter^{3, 4}	9.953 Gb/s	–	–	0.17	UI
T_J8.0	Total jitter^{3, 4}	8.0 Gb/s	–	–	0.32	UI
D_J8.0	Deterministic jitter^{3, 4}	8.0 Gb/s	–	–	0.17	UI
T_J6.6	Total jitter^{3, 4}	6.6 Gb/s	–	–	0.30	UI
D_J6.6	Deterministic jitter^{3, 4}	6.6 Gb/s	–	–	0.15	UI
T_J5.0	Total jitter^{3, 4}	5.0 Gb/s	–	–	0.30	UI
D_J5.0	Deterministic jitter^{3, 4}	5.0 Gb/s	–	–	0.15	UI
T_J4.25	Total jitter^{3, 4}	4.25 Gb/s	–	–	0.30	UI
D_J4.25	Deterministic jitter^{3, 4}	4.25 Gb/s	–	–	0.15	UI
T_J4.0	Total jitter^{3, 4}	4.0 Gb/s	–	–	0.32	UI
D_J4.0	Deterministic jitter^{3, 4}	4.0 Gb/s	–	–	0.16	UI
T_J3.20	Total jitter^{3, 4}	3.20 Gb/s⁵	–	–	0.20	UI
D_J3.20	Deterministic jitter^{3, 4}	3.20 Gb/s⁵	–	–	0.10	UI
T_J2.5	Total jitter^{3, 4}	2.5 Gb/s⁶	–	–	0.20	UI
D_J2.5	Deterministic jitter^{3, 4}	2.5 Gb/s⁶	–	–	0.10	UI
T_J1.25	Total jitter^{3, 4}	1.25 Gb/s7	–	–	0.15	UI
D_J1.25	Deterministic jitter^{3, 4}	1.25 Gb/s7	–	–	0.06	UI
T_J500	Total jitter^{3, 4}	500 Mb/s⁸	–	–	0.10	UI
D_J500	Deterministic jitter^{3, 4}	500 Mb/s⁸	–	–	0.03	UI
Using same REFCLK input with TX phase alignment enabled for up to four consecutive transmitters (one fully populated GTH Quad) at the maximum line rate. Using QPLL_FBDIV = 40, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations. Using CPLL_FBDIV = 2, 20-bit internal data width. These values are NOT intended for protocol specific compliance determinations. All jitter values are based on a bit-error ratio of 10^–12. CPLL frequency at 3.2 GHz and TXOUT_DIV = 2. CPLL frequency at 2.5 GHz and TXOUT_DIV = 2. CPLL frequency at 2.5 GHz and TXOUT_DIV = 4. CPLL frequency at 2.0 GHz and TXOUT_DIV = 8.

Table 8. GTH Transceiver Receiver Switching Characteristics
Symbol	Description	Condition	Min	Typ	Max	Units
F_GTHRX	Serial data rate		0.500	–	F_GTHMAX	Gb/s
R_XSST	Receiver spread-spectrum tracking¹	Modulated at 33 kHz	–5000	–	0	ppm
R_XRL	Run length (CID)		–	–	256	UI
R_XPPMTOL	Data/REFCLK PPM offset tolerance	Bit rates ≤ 6.6 Gb/s	–1250	–	1250	ppm
		Bit rates > 6.6 Gb/s and ≤ 8.0 Gb/s	–700	–	700	ppm
		Bit rates > 8.0 Gb/s	–200	–	200	ppm
SJ Jitter Tolerance²
J_{T_SJ16.375}	Sinusoidal jitter (QPLL)³	16.375 Gb/s	0.30	–	–	UI
J_{T_SJ15.0}	Sinusoidal jitter (QPLL)³	15.0 Gb/s	0.30	–	–	UI
J_{T_SJ14.1}	Sinusoidal jitter (QPLL)³	14.1 Gb/s	0.30	–	–	UI
J_{T_SJ13.1}	Sinusoidal jitter (QPLL)³	13.1 Gb/s	0.30	–	–	UI
J_{T_SJ12.5}	Sinusoidal jitter (QPLL)³	12.5 Gb/s	0.30	–	–	UI
J_{T_SJ11.3}	Sinusoidal jitter (QPLL)³	11.3 Gb/s	0.30	–	–	UI
J_{T_SJ10.32_QPLL}	Sinusoidal jitter (QPLL)³	10.32 Gb/s	0.30	–	–	UI
J_{T_SJ10.32_CPLL}	Sinusoidal jitter (CPLL)³	10.32 Gb/s	0.30	–	–	UI
J_{T_SJ9.953_QPLL}	Sinusoidal jitter (QPLL)³	9.953 Gb/s	0.30	–	–	UI
J_{T_SJ9.953_CPLL}	Sinusoidal jitter (CPLL)³	9.953 Gb/s	0.30	–	–	UI
J_{T_SJ8.0}	Sinusoidal jitter (QPLL)³	8.0 Gb/s	0.42	–	–	UI
J_{T_SJ6.6_CPLL}	Sinusoidal jitter (CPLL)³	6.6 Gb/s	0.44	–	–	UI
J_{T_SJ5.0}	Sinusoidal jitter (CPLL)³	5.0 Gb/s	0.44	–	–	UI
J_{T_SJ4.25}	Sinusoidal jitter (CPLL)³	4.25 Gb/s	0.44	–	–	UI
J_{T_SJ3.2}	Sinusoidal jitter (CPLL)³	3.2 Gb/s⁴	0.45	–	–	UI
J_{T_SJ2.5}	Sinusoidal jitter (CPLL)³	2.5 Gb/s⁵	0.30	–	–	UI
J_{T_SJ1.25}	Sinusoidal jitter (CPLL)³	1.25 Gb/s⁶	0.30	–	–	UI
J_{T_SJ500}	Sinusoidal jitter (CPLL)³	500 Mb/s⁷	0.30	–	–	UI
SJ Jitter Tolerance with Stressed Eye²
J_{T_TJSE3.2}	Total jitter with stressed eye⁸	3.2 Gb/s	0.70	–	–	UI
J_{T_TJSE6.6}	Total jitter with stressed eye⁸	6.6 Gb/s	0.70	–	–	UI
J_{T_SJSE3.2}	Sinusoidal jitter with stressed eye⁸	3.2 Gb/s	0.10	–	–	UI
J_{T_SJSE6.6}	Sinusoidal jitter with stressed eye⁸	6.6 Gb/s	0.10	–	–	UI
Using RXOUT_DIV = 1, 2, and 4. All jitter values are based on a bit error ratio of 10^–12. The frequency of the injected sinusoidal jitter is 80 MHz. CPLL frequency at 3.2 GHz and RXOUT_DIV = 2. CPLL frequency at 2.5 GHz and RXOUT_DIV = 2. CPLL frequency at 2.5 GHz and RXOUT_DIV = 4. CPLL frequency at 2.0 GHz and RXOUT_DIV = 8. Composite jitter with RX equalizer enabled. DFE disabled.

GTH Transceiver Switching Characteristics - DS931

Artix UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS931)