Revision History - DS930

Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930)
Document ID
DS930
Release Date
2025-12-19
Revision
1.2 English

The following table shows the revision history for this document.

Section Revision Summary
12/19/2025 Version 1.2
Table 1 and Table 1 Added VCCAUX_XP5IO to description of VCCAUX_IO.
Table 1 Updated notes 5 and 6.
Table 1 Updated description of R for calibrated programmable on-die termination (DCI) in XP5IO I/O banks.
Table 1, Table 1, Table 1, Table 1, and Table 1 Replaced XCSU50P and XCSU55P with XCSU45P and XCSU60P.
Table 3 Added note 4.
Table 4 Updated VIL max and VIH min for POD10 and POD12.
Table 6
  • Updated title to HD I/O banks.
  • Removed LVDS and LVDS_25 notes.
Table 7 Added table.
Table 1 Updated to Vivado Design Suite 2025.2.
FPGA Logic Performance Characteristics Added bullet about input/output registers in HD I/O banks.
Table 6 Added PHY rates for -1 (0.72V) speed grade.
Table 1 Removed TIOL_IDELAY_RESOLUTION/TIOL_ODELAY_RESOLUTION row.
Table 1 Updated TSCCKL and TSCCKH to 2.0 ns.
Table 2 Changed TQSPICSCLK and TQSPICLKCS for SPI clock ≥ 51 MHz and SPI clock < 51 MHz to 6 ns.
Table 3 Changed TOSPICSCLK and TOSPICLKCS for DDR > 51 MHz, SDR > 51 MHz, and SDR < 51 MHz to 8 ns.
06/13/2025 Version 1.1
Table 1
  • Added minimum and maximum values for VREF.
  • Added minimum, typical, and maximum values for R in XP5IO I/O banks.
Table 3 Populated table.
Table 1 Added quiescent supply currents for XCSU10P, XCSU25P, and XCSU35P.
Table 1 Updated ICCINTMIN for XCSU10P, XCSU25P, and XCSU35P to 560 mA.
Table 5 and Table 14 Populated entries for LVSTL06_12 and LVSTL11 standards.
Table 12 Populated entries for DIFF_LVSTL06_12 and DIFF_LVSTL11 standards.
Table 16 Populated table.
Table 1 Updated to Vivado Design Suite 2025.1.
Table 1 Moved XCSU10P, XCSU25P, and XCSU35P to production.
FPGA Logic Performance Characteristics
  • Removed XP5IO and LVDS from introductory paragraphs.
  • In Table 1, updated table title and replaced LVDS RX DDR and LVDS RX SDR with TX DDR, TX SDR, RX DDR, and RX SDR.
  • Added Table 3.
  • Revised Table 2.
Table 1
  • Populated values for maximum frequency parameters.
  • Updated block RAM and FIFO clock-to-out delays.
Table 1 Revised table.
Table 1 Added subrows for PLLE4XP to PLL_FOUTMAX and PLL_FOUTMIN.
Table 1
  • Updated description of TPL and updated value to 6 ms for all speed grades.
  • Updated FCCU_IRO_CLK for -1 (0.72V) to 127.5 MHz.
  • Updated description and units of FCCU_IRO_CLK and FPMC_IRO_CLK.
  • Updated FMCCK for master OSPI (x8) SDR CCLK frequency for -2 and -1 at 0.85V to 125 MHz and added subrow for master OSPI (x8) DDR CCLK frequency.
  • Updated FSCCK for all speed grades to 200 MHz and added subrow for slave serial daisy chain.
  • Updated FEMCCK for master SPI for -2 and -1 at 0.85V to 166 MHz and master OSPI for -2 and -1 at 0.85V to 125 MHz.
  • Added values for TSCSCLK/SCLKCS.
  • Updated FEFUSE_CLK description and added FEFUSE_CLKTOL.
  • Added part numbers to TDCI_MATCH description.
  • Added notes 3, 4, and 5.
Table 2
  • Updated descriptions.
  • Updated FQSPI_CLK to 166 MHz.
  • Replaced TQSPICKO with TQSPIDVC and TQSPICDX.
  • Added minimum values for all parameters.
Table 3
  • Updated descriptions.
  • Updated maximum FOSPI_CLK for DDR > 51 MHz to 125 MHz.
  • Replaced TOSPICKO with TOSPIDVC and TOSPICDX.
  • Updated maximum FOSPI_CLK for SDR > 51 MHz to 125 MHz.
  • Added minimum values for all parameters.
01/24/2025 Version 1.0
Initial release. N/A