LVDS DC Specifications (LVDS15) - DS930

Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930)
Document ID
DS930
Release Date
2025-12-19
Revision
1.2 English

The LVDS15 standard is available in the XP5IO I/O banks. See the Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861) for more information.

Table 1. LVDS_15 DC Specifications
Symbol DC Parameter Conditions Min Typ Max Units
VCCO 1 Supply voltage 1.455 1.500 1.545 V
VODIFF 2 Differential output voltage:

(Q – Q), Q = High

(Q – Q), Q = High

 RT = 100Ω across Q and Q signals 247 350 454 mV
VOCM 2 Output common-mode voltage RT = 100Ω across Q and Q signals 1.000 1.200 1.320 V
VIDIFF 3 Differential input voltage:

(Q – Q), Q = High

(Q – Q), Q = High

 100 350 600 3 mV
VICM_DC 4 Input common-mode voltage (DC coupling) 0.300 1.200 1.320 V
VICM_AC 5 Input common-mode voltage (AC coupling) 200 – 330 mV
  1. In XP5IO banks, when LVDS is used with input-only functionality, it can be placed in a bank where the VCCO levels are different from the specified level only if internal differential termination is not used. In this scenario, VCCO must be chosen to ensure the input pin voltage levels do not violate the Recommended Operating Condition (Table 1) specification for the VIN I/O pin voltage.
  2. VOCM and VODIFF values are for LVDS_PRE_EMPHASIS = FALSE.
  3. Maximum VIDIFF value is specified for the maximum VICM specification. With a lower VICM, a higher VDIFF is tolerated only when the recommended operating conditions and overshoot/undershoot VIN specifications are maintained.
  4. Input common mode voltage for DC coupled configurations. EQUALIZATION = EQ_NONE (Default).
  5. AC coupling with external bias and external differential termination with EQUALIZATION settings enabled. EQUALIZATION = EQ_LEVEL0, EQ_LEVEL1, EQ_LEVEL2, EQ_LEVEL3, or EQ_LEVEL4, any setting except EQ_NONE.