Integrated Interface Block for PCI Express Designs - DS930

Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930)

Document ID
DS930
Release Date
2025-12-19
Revision
1.2 English

More information and documentation on solutions for PCI Express® designs can be found at PCI Express . The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists how many PCIE4CE blocks are in each Spartan UltraScale+ FPGA. For supported modes, link widths, and link speeds, see the UltraScale+ Devices Integrated Block for PCI Express LogiCORE IP Product Guide (PG213).

Table 1. Maximum Performance for PCIE4CE-based PCI Express Designs
Symbol Description Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -1
FPIPECLK Pipe clock maximum frequency 250.00 250.00 250.00 MHz
FCORECLK Core clock maximum frequency 500.00 500.00 250.00 MHz
FDRPCLK DRP clock maximum frequency 250.00 250.00 250.00 MHz
FMCAPCLK MCAP clock maximum frequency 125.00 125.00 125.00 MHz