FPGA Logic Performance Characteristics

This section provides the performance characteristics of some common functions and designs implemented in the Spartan UltraScale+ FPGAs. These values are subject to the same guidelines as the AC Switching Characteristics section.

In each of the following performance tables, the I/O bank type is either high performance (HP) or high density (HD).

In component mode:

For the input/output registers in HP I/O banks, the Vivado tools limit clock frequencies to 312.9 MHz for all speed grades.
For IDDR in HP I/O banks, Vivado tools limit clock frequencies to 625.0 MHz for all speed grades.
For ODDR in HP I/O banks, Vivado tools limit clock frequencies to 625.0 MHz for all speed grades.
For input/output registers (including IDDR and ODDR) in HD I/O banks, the Vivado tools limit clock frequencies to 200 MHz for all speed grades.

Table 1. HD IOL and HP Component Mode Performance
Description	I/O Bank Type	Speed Grade and V_CCINT Operating Voltages						Units
		0.85V				0.72V
		-2		-1		-1
		Min	Max	Min	Max	Min	Max
TX DDR (OSERDES 4:1, 8:1)	HP	0	1250	0	1250	0	1250	Mb/s
TX SDR (OSERDES 2:1, 4:1)	HP	0	625	0	625	0	625	Mb/s
RX DDR (ISERDES 1:4, 1:8)	HP	0	1250	0	1250	0	1250	Mb/s
RX SDR (ISERDES 1:2, 1:4)	HP	0	625	0	625	0	625	Mb/s
TX DDR	HD	0	400	0	400	0	400	Mb/s
TX SDR	HD	0	200	0	200	0	200	Mb/s
RX DDR	HD	0	400	0	400	0	400	Mb/s
RX SDR	HD	0	200	0	200	0	200	Mb/s
The maximum performance figures listed here assume high-speed design practices. These practices include using an optimal clocking topology, an IOSTANDARD and physical link capable of operating at the target speeds, and matching data arrival times at the receiver (the PCB design must account for package skew). Because HDIO pins do not have clock alignment circuitry, clock-to-data phase alignment must be managed on the PCB side. The design must also support the timing analysis provided by the Vivado Design Suite.

Table 2. XP5IO PHY I/O Performance
Description^{1, 2}	Data Width	Performance as a Function of Speed Grade and Operating Voltage (V_CCINT)						Units
		0.85V				0.72V
		-2		-1		-1
		Min	Max	Min	Max	Min	Max
TX DDR	8	268.75	1600	268.75	1600	268.75	1600	Mb/s
	4	268.75	1600	268.75	1600	268.75	1260	Mb/s
	2	268.75	800	268.75	800	268.75	630	Mb/s
RX DDR³	8	268.75	1600	268.75	1600	268.75	1600	Mb/s
	4	268.75	1600	268.75	1600	268.75	1260	Mb/s
	2	268.75	800	268.75	800	268.75	630	Mb/s
XP5IO PHY I/O is supported through the IP available with the Vivado Design Suite. The performance values assume a source-synchronous interface. Package skews are not included and should be removed through PCB routing. SDR specifications are a subset of the DDR specifications.

Table 3. Native Mode Performance
Description^{1, 2}	DATA_WIDTH	I/O Bank Type	Speed Grade and V_CCINT Operating Voltages						Units
			0.85V				0.72V
			-2		-1		-1
			Min	Max	Min	Max	Min	Max
TX DDR (TX_BITSLICE)	8	HP	375	1600	375	1600	375	1600	Mb/s
TX DDR (TX_BITSLICE)	4	HP	375	1600	375	1600	375	1260	Mb/s
TX SDR (TX_BITSLICE)	8	HP	187.5	800	187.5	800	187.5	800	Mb/s
TX SDR (TX_BITSLICE)	4	HP	187.5	800	187.5	800	187.5	630	Mb/s
RX DDR (RX_BITSLICE)³	8	HP	375	1600⁴	375	1600⁴	375	1600⁴	Mb/s
RX DDR (RX_BITSLICE)³	4	HP	375	1600⁴	375	1600⁴	375	1260⁴	Mb/s
RX SDR (RX_BITSLICE)³	8	HP	187.5	800	187.5	800	187.5	800	Mb/s
RX SDR (RX_BITSLICE)³	4	HP	187.5	800	187.5	800	187.5	630	Mb/s
Native mode is supported through the High-Speed SelectIO Interface Wizard available with the Vivado Design Suite. The performance values assume a source-synchronous interface. PLL settings can restrict the minimum allowable data rate. For example, when using the PLL with CLKOUTPHY_MODE = VCO_HALF the minimum frequency is PLL_F_VCOMIN/2. Receivers are typically bounded with certain applications to achieve maximum performance. Package skews are not included and should be removed through PCB routing. Asynchronous receiver performance is limited to 1300 Mb/s for -3/-2 speed grades and to 1250 Mb/s for -1 speed grades.

Table 4. MIPI D-PHY Performance
Description	I/O Bank Type	Packages	Speed Grade and V_CCINT Operating Voltages			Units
			0.85V		0.72V
			-2	-1	-1
Maximum MIPI D-PHY transmitter or receiver data rate per lane¹	XP5IO I/O	SBVF784 SBVG784 SBVA1024 NBVA1089	3200	3200	–	Mb/s
	XP5IO I/O	CMVB529 SBVC529	2500	2500	–	Mb/s
	HP I/O	NBVA1089	2500	2500	2500	Mb/s
		SBVF784 SBVG784 SBVA1024	2500	2500	2500	Mb/s
		CMVA361 CMVA529 CMVB529 SBVC529 SBVB625	1500	1500	1500	Mb/s
For applicable conditions, the lower maximum data rate applies.

Table 5. LVDS Native-Mode 1000BASE-X Support
Description¹	I/O Bank Type	Speed Grade and V_CCINT Operating Voltages
		0.85V		0.72V
		-2	-1	-1
1000BASE-X	HP	Yes
1000BASE-X support is based on the IEEE Standard for CSMA/CD Access Method and Physical Layer Specifications (IEEE Std 802.3-2008).

The following table provides the maximum data rates for applicable memory standards using the Spartan UltraScale+ FPGA memory PHY. Refer to Memory Solutions for the complete list of memory interface standards supported and detailed specifications. The final performance of the memory interface is determined through a complete design implemented in the Vivado Design Suite, following guidelines in the UltraScale Architecture PCB Design User Guide (UG583), electrical analysis, and characterization of the system.

Table 6. Maximum Physical Interface (PHY) Rate for Integrated Memory Interface Controller
Memory Standard	I/O Bank Type	DRAM Type	Packages	Speed Grade and V_CCINT Operating Voltages			Units
				0.85V		0.72V
				-2	-1	-1
LPDDR5/LPDDR5x	XP5IO	Single rank component	SBVF784 SBVG784 SBVA1024 NBVA1089	4267	3733	3200	Mb/s
LPDDR5/LPDDR5x	XP5IO	Single rank component	CMVB529 SBVC529	2667	2667	2667	Mb/s
LPDDR4X	XP5IO	Single rank component	SBVF784 SBVG784 SBVA1024 NBVA1089	4267	3733	3200	Mb/s
LPDDR4X	XP5IO	Single rank component	CMVB529 SBVC529	2667	2667	2667	Mb/s

Table 7. Maximum Physical Interface (PHY) Rate for Soft Memory Interface Controller
Memory Standard	I/O Bank Type	DRAM Type	Packages	Speed Grade and V_CCINT Operating Voltages			Units
				0.85V		0.72V
				-2	-1	-1
DDR4	HP I/O	Single rank component	SBVF784 SBVG784 SBVA1024 NBVA1089	2400	2133	1866	Mb/s
DDR4	HP I/O	Single rank component	CMVA361 CMVA529 CMVB529 SBVC529 SBVB625	1866	1866	1866	Mb/s

FPGA Logic Performance Characteristics - DS930

Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930)