Configuration Switching Characteristics - DS930

Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930)
Document ID
DS930
Release Date
2025-12-19
Revision
1.2 English
Table 1. Configuration Switching Characteristics
Symbol Description Speed Grade and VCCINT Operating Voltages Units
0.85V 0.72V
-2 -1 -1
Power-up Timing Characteristics
TPL Program latency time from PROGRAM_B High to INIT_B High-Z 6 6 6 ms, Max
TPOR 1, 2 Power-on reset time from start of power-up ramp to INIT_B High-Z (40 ms maximum ramp rate) 65 65 65 ms, Max
0 0 0 ms, Min
Power-on reset time from start of power-up ramp to INIT_B High-Z with POR override (2 ms maximum ramp rate) 15 15 15 ms, Max
5 5 5 ms, Min
TPROGRAM PROGRAM_B Low pulse width 250 250 250 ns, Min
OSC Core and IRO Clock Switching
FOSC_CORE_CLK 3 Internal clock source core configuration frequency 510 510 510 MHz, Typ
Internal clock source core configuration tolerance ±15 ±15 ±15 %, Max
FCCU_IRO_CLK 3, 4 Internal configuration control unit clock maximum frequency 170 170 127.5 MHz, Typ
FPMC_IRO_CLK 3, 5 Internal PMC control clock maximum frequency 255 255 255 MHz, Typ
AXI32 Clock Switching
FAXI_CLK PL AXI32 clock (AXICLK) to PMC 200 200 200 MHz, Max
CCLK Output (Master Configuration Modes)
TMCCKDC Master CCLK clock duty cycle 45/55 45/55 45/55 %, Min/Max
FMCCK Master SPI (x1/x2/x4) CCLK frequency 166 166 125 MHz, Max
Master OSPI (x8) SDR CCLK frequency 125 125 125
Master OSPI (x8) DDR CCLK frequency 125 125 125
FMCCK_START Master CCLK frequency at start of configuration 21 21 21 MHz, Typ
FMCCKTOL Frequency tolerance, master mode with respect to nominal CCLK ±15 ±15 ±15 %, Max
CCLK Input (Slave Configuration Modes)
TSCCKL Slave CCLK clock minimum Low time 2.0 2.0 2.0 ns, Min
TSCCKH Slave CCLK clock minimum High time 2.0 2.0 2.0 ns, Min
FSCCK Slave serial CCLK frequency for write 200 200 200 MHz, Max
Slave serial daisy chain CCLK frequency for write 50 50 50
Slave SelectMAP CCLK frequency for write 200 200 200
EMCCLK Input (Master Configuration Modes)
TEMCCKDC External master CCLK duty cycle 45/55 45/55 45/55 %, Min/Max
FEMCCK External master configuration clock (EMCCLK) frequency with master SPI (x1/x2/x4) 166 166 125 MHz, Max
External master configuration clock (EMCCLK) frequency with master OSPI (x1/x8) 125 125 125
Internal Configuration Access Port
FICAPCK Internal configuration access port (ICAPE3) 200 200 150 MHz, Max
Slave Serial Mode Programming Switching
TDCCK/TCCKD DIN setup/hold from CCLK rising edge 3.0/0 3.0/0 4.0/0 ns, Min
TCCO CCLK falling edge to DOUT 8.0 8.0 8.0 ns, Max
TSCSCLK/SCLKCS Serial chip select (CS_B) setup and hold to CCLK rising edge 4.0/0.0 4.0/0.0 4.5/0.0 ns, Min
CREADYCS READY deassertion to chip select deassertion 24 24 24 clock cycles, Max
Slave SelectMAP Mode Programming Switching
TSMAPDCLK/SMAPCLKD SelectMAP data (D[31:00]) setup and hold to CCLK rising edge 4.0/0.0 4.0/0.0 4.5/0.0 ns, Min
TSMAPCSCLK/SMAPCLKCS SelectMAP chip select (CSI_B) setup and hold to CCLK rising edge 4.0/0.0 4.0/0.0 4.5/0.0 ns, Min
TSMAPRWCLK/SMAPCLKRW SelectMAP read write (RDWR_B) setup and hold to CCLK rising edge 9.0/0.0 9.0/0.0 10.0/0.0 ns, Min
TSMAPCLKO SelectMAP CCLK rising edge to data output 8 8 8 ns, Max
CSMAPBUSYCS SelectMAP BUSY assertion to CSI_B deassertion 24 24 24 clock cycles, Max
Boundary-Scan Port Timing Specifications
TTAPTCK/TTCKTAP TMS and TDI setup/hold to/from TCK rising edge 3.0/2.0 3.0/2.0 4.0/2.0 ns, Min
TTCKTDO TCK falling edge to TDO output 7 7 8 ns, Max
FTCK TCK frequency 66 66 50 MHz, Max
eFUSE Clock Switching
FEFUSE_CLK Internal EFUSE_CLK frequency for programming source from DNA_PORTE2.CLK, FUSE_CLK, or EMCCLK 25/200 25/200 25/200 MHz, Min/Max
FEFUSE_CLKTOL Internal EFUSE_CLK frequency tolerance for programming source from DNA_PORTE2.CLK, FUSE_CLK, or EMCCLK ±5 ±5 ±5 %, Max
DNA_PORTE2 Switching
FDNACK DNA_PORTE2 CLK frequency 200 200 175 MHz, Max
STARTUPE3 Ports
TUSRCCLKO STARTUPE3 USRCCLKO input port to CCLK pin output delay 0.25/6.50 0.25/7.50 0.25/9.00 ns, Min/Max
TDO DO[3:0] ports to D03-D00 pins output delay 0.25/7.70 0.25/8.40 0.25/10.00 ns, Min/Max
TDTS DTS[3:0] ports to D03-D00 pins 3-state delays 0.25/7.70 0.25/8.40 0.25/10.00 ns, Min/Max
TFCSBO FCSBO port to FCS_B pin output delay 0.25/7.50 0.25/8.40 0.25/9.80 ns, Min/Max
TFCSBTS FCSBTS port to FCS_B pin 3-state delay 0.25/7.50 0.25/8.40 0.25/9.80 ns, Min/Max
TUSRDONEO USRDONEO port to DONE pin output delay 0.25/9.40 0.25/10.50 0.25/12.10 ns, Min/Max
TUSRDONETS USRDONETS port to DONE pin 3-state delay 0.25/9.40 0.25/10.50 0.25/12.10 ns, Min/Max
TDI D03-D00 pins to DI[3:0] ports input delay 0.5/3.1 0.5/3.5 0.5/4.0 ns, Min/Max
FCFGMCLK STARTUPE3 CFGMCLK output frequency 50 50 50 MHz, Typ
FCFGMCLKTOL STARTUPE3 CFGMCLK output frequency tolerance ±15 ±15 ±15 %, Max
TDCI_MATCH Specifies a stall in the start-up cycle until the digitally controlled impedance (DCI) match signals are asserted for SU10P, SU15P, and SU35P devices 4 4 4 ms, Max
  1. The TPOR specification begins when the last of the monitored supplies (VCCINT, VCCBRAM, VCCAUX, VCCO_0) reaches 95% of its recommended operating condition voltage.
  2. The TPOR time is determined by the POR_OVERRIDE input pin which must be tied to VCCINT or GND. The POR_OVERRIDE pin can be tied to VCCINT for POR override only when the monitored supplies ramp within the specified 2 ms maximum ramp rate. Otherwise, POR_OVERRIDE must be tied to GND.
  3. The internal clock source core configuration tolerance applies to FOSC_CORE_CLK, FCCU_IRO_CLK, and FPMC_IRO_CLK.
  4. The maximum FCCU_IRO_CLK test condition is with the minimum supported CCU_IRO_CLK_CTRL.DIVISOR = 3 setting.
  5. The maximum FPMC_MAIN_IRO_CLK test condition is with the minimum supported PMC_MAIN_IRO_CLK_CTRL.DIVISOR = 2 setting.
Table 2. Master SPI Mode Programming Switching
Symbol Description 1, 2 Min Max Units
SPI clock frequency operating at ≥ 51 MHz
FQSPI_CLK CCLK frequency 51 166 MHz
TSPIIVW Input valid data window 0.4 – UI
TQSPIDVC Output data valid before CCLK rising edge 2.1 – ns
TQSPICDX Output data valid after CCLK rising edge 2.1 – ns
TQSPICSCLK Chip select asserted to next CCLK rising edge 6 – ns
TQSPICLKCS CCLK rising edge to chip select deasserted 6 – ns
SPI clock frequency operating at < 51 MHz
FQSPI_CLK CCLK frequency 17 50 MHz
TQSPIDCK Setup time to CCLK rising edge, all inputs 0 – ns
TQSPICKD Hold time from CCLK rising edge, all inputs 6 – ns
TQSPIDVC Output data valid before CCLK rising edge 6 – ns
TQSPICDX Output data valid after CCLK rising edge 6 – ns
TQSPICSCLK Chip select asserted to next CCLK rising edge 6 – ns
TQSPICLKCS CCLK rising edge to chip select deasserted 6 – ns
  1. The test conditions are configured for the Master SPI configuration mode 4-bit interface with a 12 mA drive strength, fast slew rate, and load conditions (15 pF/30 pF for an SPI 4-bit interface clock frequency up to 100 MHz and 15 pF for clock frequency >100 MHz), tested at 1.8V.
  2. 30 pF loads are for QSPI dual-stacked.
Table 3. Master Octal-SPI Mode Programming Switching
Symbol Description 1 Min Max Units
Octal-SPI clock frequency operating at DDR > 51 MHz
FOSPI_CLK CCLK frequency 51 125 MHz
TOSPIIVW Input valid window within the DQS pulse 0.5 – UI
TOSPIDVC Output data valid before CCLK edge 0.8 – ns
TOSPICDX Output data valid after CCLK edge 0.8 – ns
TOSPICSCLK Chip select asserted to next CCLK rising edge 8 – ns
TOSPICLKCS CCLK rising edge to chip select deasserted 8 – ns
Octal-SPI clock frequency operating at SDR > 51 MHz
FOSPI_CLK CCLK frequency 51 125 MHz
TOSPIIVW Input valid data window 0.4 – UI
TOSPIDVC Output data valid before CCLK rising edge 2.1 – ns
TOSPICDX Output data valid after CCLK rising edge 2.1 – ns
TOSPICSCLK Chip select asserted to next CCLK rising edge 8 – ns
TOSPICLKCS CCLK rising edge to chip select deasserted 8 – ns
Octal-SPI clock frequency operating at SDR < 51 MHz
FOSPI_CLK CCLK frequency 17 50 MHz
TOSPIDCK Setup time to CCLK rising edge, all data inputs 0 – ns
TOSPICKD Hold time from CCLK rising edge, all data inputs 6 – ns
TOSPIDVC Output data valid before CCLK rising edge 6 – ns
TOSPICDX Output data valid after CCLK rising edge 6 – ns
TOSPICSCLK Chip select asserted to next CCLK rising edge 8 – ns
TOSPICLKCS CCLK rising edge to chip select deasserted 8 – ns
  1. The test conditions are configured for the Octal-SPI interface with a 12 mA drive strength, fast slew rate, and 12 pF load. The maximum Octal-SPI device clock frequency under different load conditions are 150 MHz for a 20 pF load and 100 MHz for a 40 pF load.