Absolute Maximum Ratings - DS930

Spartan UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS930)

Document ID
DS930
Release Date
2025-12-19
Revision
1.2 English
Table 1. Absolute Maximum Ratings
Symbol Description 1 Min Max Units

FPGA Logic

VCCINT Internal supply voltage –0.500 1.000 V
VCCINT_IO 2 Internal supply voltage for the I/O banks –0.500 0.980 V
VCCAUX 3 Auxiliary supply voltage –0.500 1.960 V
VCCBRAM 2 Supply voltage for the block RAM and UltraRAM –0.500 0.980 V
VCCO Output drivers supply voltage for HD I/O banks –0.500 3.400 V
Output drivers supply voltage for HP I/O banks and configuration bank 0 –0.500 1.960 V
Output drivers supply voltage for XP5IO banks –0.500 1.650 V
VCCAUX_IO 3 Auxiliary supply voltage for the I/O banks. Available as VCCAUX_HDIO for HD I/O banks, VCCAUX_HPIO for HP I/O banks, and VCCAUX_XP5IO for XP5IO banks. –0.500 1.960 V
VREF Input reference voltage for HP I/O banks –0.500 2.000 V
VIN 4, 5 , 6 , 7 I/O input voltage for HD I/O, HP I/O, and XP5IO I/O banks –0.550 VCCO + 0.550 V
IDC Available output current at the pad –20 20 mA
IRMS Available RMS output current at the pad –20 20 mA

GTH Transceiver 8

VMGTAVCC Analog supply voltage for transceiver circuits –0.500 1.000 V
VMGTAVTT Analog supply voltage for transceiver termination circuits –0.500 1.300 V
VMGTVCCAUX Auxiliary analog Quad PLL (QPLL) voltage supply for transceivers –0.500 1.900 V
VMGTREFCLK Transceiver reference clock absolute input voltage –0.500 1.300 V
VMGTAVTTRCAL Analog supply voltage for the resistor calibration circuit of the transceiver column –0.500 1.300 V
VIN Receiver (RXP/RXN) and transmitter (TXP/TXN) absolute input voltage –0.500 1.200 V
IDCIN-FLOAT DC input current for receiver input pins DC coupled RX termination = floating 9 10 mA
IDCIN-MGTAVTT DC input current for receiver input pins DC coupled RX termination = VMGTAVTT 10 mA
IDCIN-GND DC input current for receiver input pins DC coupled RX termination = GND 0 mA
IDCIN-PROG DC input current for receiver input pins DC coupled RX termination = programmable 10 0 mA
IDCOUT-FLOAT DC output current for transmitter pins DC coupled RX termination = floating 6 mA
IDCOUT-MGTAVTT DC output current for transmitter pins DC coupled RX termination = VMGTAVTT 6 mA

System Monitor

VCCADC System Monitor supply relative to GNDADC –0.500 2.000 V
VREFP System Monitor reference input relative to GNDADC –0.500 2.000 V

Temperature 11

TSTG Storage temperature (ambient) –65 150 °C
TSOL Maximum dry rework soldering temperature 260 °C
Maximum reflow soldering temperature for SBVC529, SBVB625, SBVF784, SBVG784, SBVA1024, and NBVA1089 packages 250 °C
Maximum reflow soldering temperature for CMVA361, CMVA529, and CMVB529 packages 245 °C
Tj Maximum junction temperature 125 °C
  1. Stresses beyond those listed under Absolute Maximum Ratings might cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time might affect device reliability.
  2. VCCINT_IO must be connected to VCCBRAM.
  3. VCCAUX_HPIO, VCCAUX_HDIO, and VCCAUX_XP5IO must be connected to VCCAUX.
  4. The lower absolute voltage specification always applies.
  5. For I/O operation, see the Spartan UltraScale+ FPGAs SelectIO Resources User Guide (UG861).
  6. When operating outside of the recommended operating conditions, refer to Table 1 and Table 2 for maximum overshoot and undershoot specifications.
  7. VIN for the POR_OVERRIDE pin is unique. POR_OVERRIDE must be connected to either GND (default) or VCCINT. See TPOR in Configuration Switching Characteristics for additional information.
  8. For more information on supported GTH transceiver terminations see the UltraScale Architecture GTH Transceivers User Guide (UG576) .
  9. AC coupled operation is not supported for RX termination = floating.
  10. DC coupled operation is not supported for RX termination = programmable.
  11. For soldering guidelines and thermal considerations, see the UltraScale and UltraScale+ FPGAs Packaging and Pinouts Product Specification (UG575).