Power Supply Requirements

Table 1 shows the minimum current, in addition to I_CCQ maximum, required by each Zynq UltraScale+ RFSoC for proper power-on and configuration. If these current minimums are met, the device powers on after all supplies have passed through their power-on reset threshold voltages. The device must not be configured until after V_CCINT is applied. Once initialized and configured, use the Xilinx Power Estimator (XPE) spreadsheet tool (download at www.amd.com/power) to estimate current drain on these supplies. XPE is also used to estimate power-on current for all supplies.

Table 1. Power-on Current by Device
I_CC Min =	I_CCINTMIN	I_{CCINT_IOMIN} + I_CCBRAMMIN	I_CCOMIN	I_CCAUXMIN + I_{CCAUX_IOMIN}	I_CCSDFECMIN	Units
I_CCQ +	I_CCINTQ +	I_CCBRAMQ + I_{CCINT_IOQ} +	I_CCOQ +	I_CCAUXQ + I_{CCAUX_IOQ} +	I_CCSDFECQ +	Units
XCZU21DR XQZU21DR	4500	770	50	320	250	mA
XCZU25DR	4500	770	50	320	250	mA
XCZU27DR	4500	770	50	320	250	mA
XCZU28DR XQZU28DR	4500	770	50	320	250	mA
XCZU29DR XQZU29DR	4500	1020	50	320	N/A	mA
XCZU39DR	4500	1020	50	320	N/A	mA
XCZU42DR	3516	602	50	261	N/A	mA
XCZU43DR	4500	1020	50	320	N/A	mA
XCZU46DR	4500	1020	50	320	250	mA
XCZU47DR	4500	1020	50	320	N/A	mA
XCZU48DR XQZU48DR	4500	1020	50	320	250	mA
XCZU49DR XQZU49DR	4500	1020	50	320	N/A	mA
XCZU63DR	3516	602	50	261	N/A	mA
XCZU64DR	3516	602	50	261	N/A	mA
XCZU65DR XQZU65DR	3516	602	50	261	N/A	mA
XCZU67DR XQZU67DR	3516	602	50	261	N/A	mA

Table 2. Power Supply Ramp Time
Symbol	Description	Min	Max	Units
T_VCCINT	Ramp time from GND to 95% of V_CCINT	0.2	40	ms
T_{VCCINT_IO}	Ramp time from GND to 95% of V_{CCINT_IO}	0.2	40	ms
T_VCCO	Ramp time from GND to 95% of V_CCO	0.2	40	ms
T_VCCAUX	Ramp time from GND to 95% of V_CCAUX	0.2	40	ms
T_VCCBRAM	Ramp time from GND to 95% of V_CCBRAM	0.2	40	ms
T_MGTAVCC	Ramp time from GND to 95% of V_MGTAVCC	0.2	40	ms
T_MGTAVTT	Ramp time from GND to 95% of V_MGTAVTT	0.2	40	ms
T_MGTVCCAUX	Ramp time from GND to 95% of V_MGTVCCAUX	0.2	40	ms
T_{VCC_PSINTFP}	Ramp time from GND to 95% of V_{CC_PSINTFP}	0.2	40	ms
T_{VCC_PSINTLP}	Ramp time from GND to 95% of V_{CC_PSINTLP}	0.2	40	ms
T_{VCC_PSAUX}	Ramp time from GND to 95% of V_{CC_PSAUX}	0.2	40	ms
T_{VCC_PSINTFP_DDR}	Ramp time from GND to 95% of V_{CC_PSINTFP_DDR}	0.2	40	ms
T_{VCC_PSADC}	Ramp time from GND to 95% of V_{CC_PSADC}	0.2	40	ms
T_{VCC_PSPLL}	Ramp time from GND to 95% of V_{CC_PSPLL}	0.2	40	ms
T_{PS_MGTRAVCC}	Ramp time from GND to 95% of V_{CC_MGTRAVCC}	0.2	40	ms
T_{PS_MGTRAVTT}	Ramp time from GND to 95% of V_{CC_MGTRAVTT}	0.2	40	ms
T_{VCCO_PSDDR}	Ramp time from GND to 95% of V_{CCO_PSDDR}	0.2	40	ms
T_{VCC_PSDDR_PLL}	Ramp time from GND to 95% of V_{CC_PSDDR_PLL}	0.2	40	ms
T_{VCCO_PSIO}	Ramp time from GND to 95% of V_{CCO_PSIO}	0.2	40	ms
T_{VADC_AVCC}	Ramp time from GND to 95% of V_{ADC_AVCC}	0.2	40	ms
T_{VADC_AVCCAUX}	Ramp time from GND to 95% of V_{ADC_AVCCAUX}	0.2	40	ms
T_{VDAC_AVCC}	Ramp time from GND to 95% of V_{DAC_AVCC}	0.2	40	ms
T_{VDAC_AVCCAUX}	Ramp time from GND to 95% of V_{DAC_AVCCAUX}	0.2	40	ms
T_{VDAC_AVTT}	Ramp time from GND to 95% of V_{DAC_AVTT}	0.2	40	ms
T_VCCSDFEC	Ramp time from GND to 95% of V_CCSDFEC	0.2	40	ms

Power Supply Requirements - DS926

Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)