PS Quad-SPI Controller Interface - DS926

Zynq UltraScale+ RFSoC Data Sheet: DC and AC Switching Characteristics (DS926)
Document ID
DS926
Release Date
2024-12-23
Revision
1.14 English
Table 1. Generic Quad-SPI Interface
Symbol Description 1 Load Conditions 2 Min Max Units
Quad-SPI device clock frequency operating at 150 MHz. Loopback enabled. 3 LVCMOS 1.8V or LVCMOS 3.3V I/O standard.
TDCQSPICLK1 Quad-SPI clock duty cycle 15 pF 45 55 %
TQSPISSSCLK1 Slave select asserted to next clock edge 15 pF 5.0 – ns
TQSPISCLKSS1 Clock edge to slave select deasserted 15 pF 5.0 – ns
TQSPICKO1 Clock to output delay, all outputs 15 pF 2.9 4.5 ns
TQSPIDCK1 Setup time, all inputs 15 pF 0.9 – ns
TQSPICKD1 Hold time, all inputs 15 pF 1.0 – ns
FQSPICLK1 Quad-SPI device clock frequency 15 pF – 150 MHz
FQSPIREFCLK1 Quad-SPI reference clock frequency 15 pF – 300 MHz
Quad-SPI device clock frequency operating at 100 MHz. Loopback enabled. 3 LVCMOS 1.8V or LVCMOS 3.3V I/O standard.
TDCQSPICLK2 Quad-SPI clock duty cycle 15 pF 45 55 %
30 pF 45 55 %
TQSPISSSCLK2 Slave select asserted to next clock edge 15 pF 5.0 – ns
30 pF 5.0 – ns
TQSPISCLKSS2 Clock edge to slave select deasserted 15 pF 5.0 – ns
30 pF 5.0 – ns
TQSPICKO2 Clock to output delay, all outputs 15 pF 3.2 7.4 ns
30 pF 3.2 7.4 ns
TQSPIDCK2 Setup time, all inputs 15 pF 2.3 – ns
30 pF 2.3 – ns
TQSPICKD2 Hold time, all inputs 15 pF 0.0 – ns
30 pF 0.0 – ns
FQSPICLK2 Quad-SPI device clock frequency 15 pF – 100 MHz
30 pF – 100 MHz
FQSPIREFCLK2 Quad-SPI reference clock frequency 15 pF – 200 MHz
30 pF – 200 MHz
Quad-SPI device clock frequency operating at 40 MHz. Loopback disabled. LVCMOS 1.8V I/O standard.
TDCQSPICLK3 Quad-SPI clock duty cycle 15 pF 45 55 %
30 pF 45 55 %
TQSPISSSCLK3 Slave select asserted to next clock edge 4 15 pF 7.0 – ns
30 pF 7.0 – ns
TQSPISCLKSS3 Clock edge to slave select deasserted 15 pF 7.0 – ns
30 pF 7.0 – ns
TQSPICKO3 Clock to output delay, all outputs 15 pF 5.2 14.8 ns
30 pF 5.2 14.8 ns
TQSPIDCK3 Setup time, all inputs 15 pF 13.4 – ns
30 pF 14.1 – ns
TQSPICKD3 Hold time, all inputs 15 pF 0.0 – ns
30 pF 0.0 – ns
FQSPIREFCLK3 Quad-SPI reference clock frequency 15 pF – 160 MHz
30 pF – 160 MHz
FQSPICLK3 Quad-SPI clock frequency 15 pF – 40 MHz
30 pF – 40 MHz
Quad-SPI device clock frequency operating at 40 MHz. Loopback disabled. LVCMOS 3.3V I/O standard.
TDCQSPICLK4 Quad-SPI clock duty cycle 15 pF 45 55 %
30 pF 45 55 %
TQSPISSSCLK4 Slave select asserted to next clock edge 4 15 pF 7.0 – ns
30 pF 7.0 – ns
TQSPISCLKSS4 Clock edge to slave select deasserted 15 pF 7.0 – ns
30 pF 7.0 – ns
TQSPICKO4 Clock to output delay, all outputs 15 pF 5.2 14.8 ns
30 pF 5.2 14.8 ns
TQSPIDCK4 Setup time, all inputs 15 pF 13.9 – ns
30 pF 14.9 – ns
TQSPICKD4 Hold time, all inputs 15 pF 0.0 – ns
30 pF 0.0 – ns
FQSPIREFCLK4 Quad-SPI reference clock frequency 15 pF – 160 MHz
30 pF – 160 MHz
FQSPICLK4 Quad-SPI clock frequency 15 pF – 40 MHz
30 pF – 40 MHz
  1. The test conditions are configured for the generic Quad-SPI interface at 150/100 MHz with a 12 mA drive strength and fast slew rate.
  2. 30 pF loads are for dual-parallel stacked or stacked modes.
  3. When the Quad-SPI clock frequency is greater than 40 MHz, the Quad-SPI feedback clock (MIO[6]) must be enabled in the processing system configuration wizard (PCW), and the associated MIO[6] (clk_for_lpbk) pin must be left unconnected on the board.
  4. TQSPISSSCLK3 and TQSPISSSCLK4 are only valid when two reference clock cycles are programmed between the chip select and clock.
Table 2. Linear Quad-SPI Interface
Symbol Description 1 Load Conditions 2 Min Max Units
Quad-SPI device clock frequency operating at 100 MHz. Loopback enabled. 3 LVCMOS 1.8V or LVCMOS 3.3V I/O standard.
TDCQSPICLK5 Quad-SPI clock duty cycle 15 pF 45 55 %
30 pF 45 55 %
TQSPISSSCLK5 Slave select asserted to next clock edge 4 15 pF 5.0 – ns
30 pF 5.0 – ns
TQSPISCLKSS5 Clock edge to slave select deasserted 15 pF 5.0 – ns
30 pF 5.0 – ns
TQSPICKO5 Clock to output delay, all outputs 15 pF 3.2 7.4 ns
30 pF 3.2 7.4 ns
TQSPIDCK5 Setup time, all inputs 15 pF 2.4 – ns
30 pF 2.4 – ns
TQSPICKD5 Hold time, all inputs 15 pF 0.0 – ns
30 pF 0.0 – ns
FQSPIREFCLK5 Quad-SPI reference clock frequency 15 pF – 200 MHz
30 pF – 200 MHz
FQSPICLK5 Quad-SPI device clock frequency 15 pF – 100 MHz
30 pF – 100 MHz
Quad-SPI device clock frequency operating at 40 MHz. Loopback disabled. LVCMOS 1.8V I/O standard.
TDCQSPICLK6 Quad-SPI clock duty cycle 15 pF 45 55 %
30 pF 45 55 %
TQSPISSSCLK6 Slave select asserted to next clock edge 15 pF 7.0 – ns
30 pF 7.0 – ns
TQSPISCLKSS6 Clock edge to slave select deasserted 15 pF 7.0 – ns
30 pF 7.0 – ns
TQSPICKO6 Clock to output delay, all outputs 15 pF 5.2 14.8 ns
30 pF 5.2 14.8 ns
TQSPIDCK6 Setup time, all inputs 15 pF 13.4 – ns
30 pF 13.4 – ns
TQSPICKD6 Hold time, all inputs 15 pF 0.0 – ns
30 pF 0.0 – ns
FQSPIREFCLK6 Quad-SPI reference clock frequency 15 pF – 160 MHz
30 pF – 160 MHz
FQSPICLK6 Quad-SPI device clock frequency 15 pF – 40 MHz
30 pF – 40 MHz
Quad-SPI device clock frequency operating at 40 MHz. Loopback disabled. LVCMOS 3.3V I/O standard.
TDCQSPICLK7 Quad-SPI clock duty cycle 15 pF 45 55 %
30 pF 45 55 %
TQSPISSSCLK7 Slave select asserted to next clock edge 15 pF 7.0 – ns
30 pF 7.0 – ns
TQSPISCLKSS7 Clock edge to slave select deasserted 15 pF 7.0 – ns
30 pF 7.0 – ns
TQSPICKO7 Clock to output delay, all outputs 15 pF 5.2 14.8 ns
30 pF 5.2 14.8 ns
TQSPIDCK7 Setup time, all inputs 15 pF 14.0 – ns
30 pF 14.0 – ns
TQSPICKD7 Hold time, all inputs 15 pF 0.0 – ns
30 pF 0.0 – ns
FQSPIREFCLK7 Quad-SPI reference clock frequency 15 pF – 160 MHz
30 pF – 160 MHz
FQSPICLK7 Quad-SPI device clock frequency 15 pF – 40 MHz
30 pF – 40 MHz
  1. The test conditions are configured for the linear Quad-SPI interface at 100 MHz with a 12 mA drive strength and fast slew rate.
  2. 30 pF loads are for stacked modes.
  3. When the Quad-SPI clock frequency is greater than 40 MHz, the Quad-SPI feedback clock (MIO[6]) must be enabled in the processing system configuration wizard (PCW), and the associated MIO[6] (clk_for_lpbk) pin must be left unconnected on the board.
  4. TQSPISSSCLK5 is only valid when two reference clock cycles are programmed between chip select and clock.