PS eMMC Standard Interface - PS eMMC Standard Interface - DS925

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)
Document_ID
DS925
Release_Date
2026-07-09
Revision
1.30 English
Table 1. eMMC Standard Interface
Symbol Description 1 Min Max Units
eMMC Standard Interface
TDCEMMCHSCLK eMMC clock duty cycle 45 55 %
TEMMCHSCKO Clock to output delay, all outputs –2.0 4.5 ns
TEMMCHSDCK Input setup time, all inputs 2.0 – ns
TEMMCHSCKD Input hold time, all inputs 2.0 – ns
FEMMCHSCLK eMMC clock frequency – 25 MHz
eMMC High-Speed SDR Interface
TDCEMMCHSCLK eMMC high-speed SDR clock duty cycle 45 55 %
TEMMCHSCKO Clock to output delay, all outputs 2 3.2 16.8 ns
TEMMCHSDIVW Input valid data window 3 0.4 – UI
FEMMCHSCLK eMMC high speed SDR clock frequency – 50 MHz
eMMC High-Speed DDR Interface
TDCEMMCDDRCLK eMMC high-speed DDR clock duty cycle 45 55 %
TEMMCDDRSCKO1 Data clock to output delay 2 2.7 7.3 ns
TEMMCDDRIVW Input valid data window 3 3.5 – ns
TEMMCDDRSCKO2 Command clock to output delay 3.2 16 ns
TEMMCDDRDCK2 Command input setup time 3.9 – ns
TEMMCDDRCKD2 Command input hold time 2.5 – ns
FEMMCDDRCLK eMMC high-speed DDR clock frequency – 50 MHz
eMMC HS200 Interface
TDCEMMCHS200CLK eMMC HS200 clock duty cycle 40 60 %
TEMMCHS200CKO Clock to output delay, all outputs 2 1.0 3.4 ns
TEMMCSDR1IVW Input valid data window 3 0.4 – UI
FEMMCHS200CLK eMMC HS200 clock frequency – 200 MHz
  1. The test conditions for eMMC standard mode use an 8 mA drive strength, fast slew rate, and a 30 pF load. For eMMC high-speed mode, the test conditions use a 12 mA drive strength, fast slew rate, and a 30 pF load. For other eMMC modes, the test conditions use a 12 mA drive strength, fast slew rate, and a 15 pF load.
  2. This specification is achieved using pre-determined DLL tuning.
  3. This specification is required for capturing input data using DLL tuning.