PS DAP Interface - PS DAP Interface - DS925

Zynq UltraScale+ MPSoC Data Sheet: DC and AC Switching Characteristics (DS925)
Document_ID
DS925
Release_Date
2026-07-09
Revision
1.30 English
Table 1. DAP Interface
Symbol Description 1, 2 Min Max Units
TPDAPDCK PS DAP input setup time 3.0 – ns
TPDAPCKD PS DAP input hold time 2.0 – ns
TPDAPCKO PS DAP clock to out delay – 10.86 ns
FPDAPCLK PS DAP clock frequency – 44 MHz
  1. The test conditions are configured to the LVCMOS 3.3V I/O standard with a 12 mA drive strength, fast slew rate, and a 15 pF load.
  2. PS DAP interface signals connect to MIO pins.