Revision History

Added note about V_IN for POR_OVERRIDE pin to Table 1 and Table 1.

In Table 1, updated notes 1 and 4, and expanded V_CCO table note into notes 5 and 6.

Updated note 8 in Table 4.

Revised the Production Specification speed file version in Table 1 to Vivado Design Suite from 2021.1 v1.27 to 2022.1 v1.28 for XCVU3P, XCVU5P, XCVU7P, XCVU9P, XCVU11P, XCVU13P, XQVU3P, XQVU7P, and XQVU11P, and from 2021.1 v1.33 to 2022.1 v1.34 for XCVU23P .

Updated MIPI D-PHY data rate for -2 (0.72V) speed grade to 1500 Mb/s in Table 3.

Updated to PCIe Gen1, 2, 3, 4 protocol in Table 1.

Added notes 1 and 2 to Table 1.

For clarity, moved the location of the specifications for internal V_REF, differential termination, and temperature diode (ideality factor and series resistance) in Table 1.

Revised the Production Specification speed file version for XCVU19P in Table 1 and Table 1 to Vivado Design Suite from 2019.2.2 v1.29 to 2020.2 v1.30.

Added the XCVU23P and XCVU57P devices where applicable in this data sheet including Table 1, Table 1, and Table 1 using Vivado Design Suite 2020.2 v1.04 for the XCVU23P, and 2020.2 v1.01 for XCVU57P.

Added the Device Pin-to-Pin Input Parameter Guidelines table for the VU19P and VU23P.

Added the VSVA1365, FSVJ1760, and FSVK2892 packages to T_SOL in Absolute Maximum Ratings.

Revised the F_EMCCK description and added Note 4 to Configuration Switching Characteristics.

Added the XCVU23P and XCVU57P devices throughout.

Revised the production software and speed specification release version for the XCVU27P -3E (V_CCINT = 0.90V) and the XCVU29P -3E (V_CCINT = 0.90V) using Vivado Design Suite 2020.1.1 v1.30 in Table 1.

Updated Table 1, Table 1, and Table 1 to production release the XCVU19P device in -2E (V_CCINT = 0.85V) and -1E (V_CCINT = 0.85V) speed/voltage grades and all packages using Vivado Design Suite 2019.2.2 v1.29.

Updated the power-on current values for XCVU19P in Table 1.

In Table 1, updated Note 2.

Added the program latency (T_PL) for the XCVU19P to Table 1.

Updated Table 1, Table 1, and Table 1 to production release:

• XCVU27P and XCVU29P devices in -3E, -2LE (V_CCINT = 0.85V), and -2LE (V_CCINT = 0.72V) speed/voltage grades and all packages using Vivado Design Suite 2019.2 v1.28

Updated Table 1, Table 1, and Table 1 to production release:

• XCVU27P and XCVU29P devices in -1E, -1I, -2E and -2I speed/voltage grades and all packages using Vivado Design Suite 2019.1.3 v1.27
• XCVU47P and XCVU49P devices in -3E, -2E, -2LE, -1E (V_CCINT = 0.85V) and -2LE (V_CCINT = 0.72V)) using Vivado Design Suite 2019.1 v1.25

Deleted GTM transceiver support for DC coupled operation in Table 1. Updated PAM4 and NRZ specifications in Table 1, Table 1, Table 7, and Table 8. Updated the specifications in Table 5. In Table 7, deleted support for TX lane-to-lane skew and TX phase alignment. Removed the GTM Transceiver Clock Output Level Specification table. Revised the GTM Transceiver Electrical Compliance table.

Added the XCVU19P device in the FSVA3824 and FSVB3824 packages where applicable.

Increased the maximum line rate of the QPLL0 -1 (V_CCINT = 0.85V) output divider 1 in Table 1 and updated Notes 4 and 5.

Revised Table 1 and the GTM Transceiver Electrical Compliance table.

Added the maximum reflow soldering temperature (T_SOL) values for the FFRC1517, FFRA2104, FFRB2104, and FFRC2104 packages in Table 1.

Updated Note 4 in Table 1.

Updated the GTM sequence in Power-On/Off Power Supply Sequencing.

• XCVU31P: 2018.3.1 v1.24 (-2E, -2LE, -1E (V_CCINT = 0.85V) and -2LE (V_CCINT = 0.72V))
• XCVU33P: 2018.3.1 v1.24 (-2E, -2LE, -1E (V_CCINT = 0.85V) and -2LE (V_CCINT = 0.72V))
• XCVU37P: 2018.3.1 v1.24 (-2E, -2LE, -1E (V_CCINT = 0.85V) and -2LE (V_CCINT = 0.72V))
• XCVU39P: 2018.3.1 v1.24 (-2E, -2LE, -1E (V_CCINT = 0.85V) and -2LE (V_CCINT = 0.72V))
• XQVU3P: 2018.3 v1.23
• XQVU7P: 2018.3.1 v1.23
• XQVU11P: 2018.3.1 v1.23

In Table 1, revised the T_STG.

Added Note 16 in Table 1.

Updated the VU3xP values in Table 1.

Added LVDS component mode notes to FPGA Logic Performance Characteristics.

Added the XCVU27P and XCVU29P devices. Also added the GTM Transceiver Specifications.

Updated the calculations in Table 1

Updated the speed specification version by device for Table 1 to Vivado Design Suite 2018.3.

Updated the V_IDIFF description in Table 1.

In Table 6, updated Note 2.

Removed PCI Express Gen4 support in Table 1 and Notes 1, Note 2, and Note 3. In Table 2, removed Notes 1, 2, 3, 4, and 5.

Added XCVU3xP data to Table 1.

In Table 2, added Note 4 to the LVDS RX DDR maximum data.

In Table 1, revised the calculated values from 322.223 to 322.266.

Revised F_ACLK and added F_HBM to Table 1.

Updated Table 1, Table 1, and Table 1 to production release the following devices in Vivado Design Suite 2018.1 v1.19.

XCVU3P: -3E (V_CCINT = 0.90V)

XCVU5P: -3E (V_CCINT = 0.90V)

XCVU7P: -3E (V_CCINT = 0.90V)

XCVU9P: -3E (V_CCINT = 0.90V)

Added Table 4 and Table 4. Added Note 2 and Note 3 to Table 3. Revised Table 1 to add specifc mode specifications and remove Note 1. Added Table 2.

Updated Table 1, Table 1, and Table 1 to production release the following devices in Vivado Design Suite 2017.4.1 v1.18.

XCVU11P: -3E (V_CCINT = 0.90V)

XCVU13P: -3E (V_CCINT = 0.90V)

Revised some of the -3E (V_CCINT = 0.90V) speed files in Table 1, Table 2, Table 3, and Table 2.

Revised the D_VPPOUT control signal in Table 1.

In Table 1, corrected the minimum voltage for the System Monitor section.

Updated Table 1, Table 1, and Table 1 to production release all the -2LE (V_CCINT = 0.85V) and -2LE (V_CCINT = 0.72V) devices/speed/temperature grades in Vivado Design Suite 2017.3.1.

Revised the F_REFCLK descriptions in Table 1.

Revised some of the -3E and -2LE (V_CCINT = 0.72V) speed files in Table 1, Table 2, Table 3, Table 2, and added package values to Table 1.

Revised the F_GTYQRANGE2 -1 speed grade minimum in Table 1. Added T_SPICCM2 and T_SPICCFC2 to Table 1.

Updated Table 1 to include maximum T_SOL

Updated Table 1, Table 1, and for dry rework and reflow soldering.Table 1 to production release the following devices/speed/temperature grades in Vivado Design Suite 2017.2.1.

XCVU11P: -2E, -2I, -1E, -1I

XCVU13P: -2E, -2I, -1E, -1I

In Table 1, revised the T_{OUTBUF_DELAY_O_PAD} -2 (V_CCINT for dry r = 0.85V) values for DIFF_SSTL135_S, DIFF_SSTL15_DCI_S, DIFF_SSTL15_S, DIFF_SSTL18_I_DCI_S, and DIFF_SSTL18_I_S.

Revised some of the -3E and -2LE (V_CCINT = 0.72V) speed files in Table 1, Table 1, Table 2, and Table 3.

Updated Table 1, Table 1, and Table 1 to production release the following devices/speed/temperature grades in Vivado Design Suite 2017.2.

XCVU5P: -2E, -2I, -1E, -1I

XCVU7P: -2E, -2I, -1E, -1I

XCVU9P: -2E, -2I, -1E, -1I

Updated Note 12 in Table 1 for clarity. In Table 1, removed unsupported voltages (2.5V and 3.3V) from I_RPU and I_RPD. Added Note 3 to Table 5. Revised the -3E and -2LE (V_CCINT = 0.72V) speed files in Table 1, Table 1, Table 1, Table 2, Table 3, and Table 2. In Table 1 removed from the input delay measurement methodology section the following class II I/O standards: SSTL135_II, SSTL15_II, SSTL18_II, DIFF_SSTL135_II, DIFF_SSTL15_II and DIFF_SSTL18_II. Updated the F_MAX symbol names and values in Table 1. Added Note 1 to Table 1. Added Note 3 to Table 1. In Table 1, updated the -2LE (V_CCINT = 0.72V) specifications for F_MCCK, F_SCCK, F_EMCCK, F_ICAPCK, T_SMDCCK/T_SMCCKD, T_SMCKCSO, T_SMCO, F_RBCCK, T_BPIDCC/T_BPICCD, and T_SPIDCC/T_SPICCD.

Updated the Summary description. In Table 1, updated Note 6, added data, and added Note 7, Note 8, and Note 9. Updated and added data to Table 1 through Table 1.

Removed the -1LI speed grade.

Updated Table 1, Table 1, and Table 1 to production release in Vivado Design Suite 2017.1 for the XCVU3P: -2E, -2I, -1E, -1I.

Updated Table 1. Added Note 1 to Table 1. Updated Table 1, Table 2, Table 1, Table 1, Table 1, Table 1, Table 1, and Table 1. Added Table 3. Added MMCM_F_{DPRCLK_MAX} to Table 1 and PLL_F_{DPRCLK_MAX} to Table 1. Updated to Vivado Design Suite 2017.1 Table 1, Table 2, Table 3, and Table 2. Added data to Table 3 and Table 1. Updated the GTY Transceiver Specifications section. Revised the Integrated Interface Block for Interlaken section. Updated the System Monitor Specifications section adding notes to the tables. Updated the Configuration Switching Characteristics section. Removed the eFUSE Programming Conditions table and added the specifications to Table 1 and Table 1. Updated the Automotive Applications Disclaimer.