High Bandwidth Memory Controller

Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923)
Document ID
DS923
Release Date
2024-08-09
Revision
1.20 English

The UltraScale Architecture and Product Data Sheet: Overview (DS890) lists the Virtex UltraScale+ FPGAs with integrated high-bandwidth memory (HBM).

Table 1. Maximum Performance for High Bandwidth Memory Controller
Symbol Description Speed Grade and VCCINT Operating Voltages Units
0.90V 0.85V 0.72V
-3 -2 -1 -2
FHBM_REF_CLK HBM controller reference clock maximum frequency 450.00 450.00 450.00 450.00 MHz
FACLK AXI interface clock maximum frequency 450.00 450.00 400.00 400.00 MHz
FAPB Advance peripheral bus (APB) clock maximum frequency 100.00 100.00 100.00 100.00 MHz
FHBM HBM maximum line rate interface to DRAM 1800 1800 1600 1800 Mb/s