GTM Transceiver Switching Characteristics

Table 1. GTM Transceiver Performance
Symbol	Description^{1, 2}	Output Divider	Speed Grade and V_CCINT Operating Voltages				Units
			0.90V	0.85V		0.72V
			-3	-2	-1	-2
			Max	Max	Max	Max
F_GTMPAM4MAX	GTM transceiver PAM4 maximum line rate	1	58.00	56.42	53.20	56.42	Gb/s
F_GTMPAM4MIN	GTM transceiver PAM4 minimum line rate	1	39.20	39.20	39.20	39.20	Gb/s
F_GTMPAM42MAX	GTM transceiver PAM4 maximum line rate	2	29.00	28.21	26.60	28.21	Gb/s
F_GTMPAM42MIN	GTM transceiver PAM4 minimum line rate	2	20.60	20.60	20.60	20.60	Gb/s
F_GTMNRZMAX	GTM transceiver NRZ maximum line rate	1	29.00	28.21	26.60	28.21	Gb/s
F_GTMNRZMIN	GTM transceiver NRZ minimum line rate	1	19.60	19.60	19.60	19.60	Gb/s
F_GTMNRZ2MAX	GTM transceiver NRZ maximum line rate	2	14.50	14.105	13.30	14.105	Gb/s
F_GTMNRZ2MIN	GTM transceiver NRZ minimum line rate	2	10.30	10.30	10.30	10.30	Gb/s
For PAM4, data rates from F_GTMPAM42MAX to 39.2 Gb/s are not available. For NRZ, data rates from F_GTMNRZ2MAX to 19.6 Gb/s are not available.

Table 2. GTM Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Symbol	Description	All Speed Grades	Units
F_GTMDRPCLK	GTMDRPCLK maximum frequency	250	MHz

Table 3. GTM Transceiver Reference Clock Switching Characteristics
Symbol	Description	Conditions	All Speed Grades			Units
Symbol	Description	Conditions	Min	Typ	Max	Units
F_GCLK	Reference clock frequency range		60	–	820	MHz
T_RCLK	Reference clock rise time	20% – 80%	–	200	–	ps
T_FCLK	Reference clock fall time	80% – 20%	–	200	–	ps
T_DCREF	Reference clock duty cycle	Transceiver PLL only	40	50	60	%

Table 4. GTM Transceiver Reference Clock Oscillator Selection Phase Noise Mask
Symbol	Description^{1, 2}	Offset Frequency	Min	Typ	Max	Units
LCPLL_REFCLKMASK	LCPLL reference clock select phase noise mask at REFCLK frequency = 156.25 MHz	10 kHz	–	–	–112	dBc/Hz
		100 kHz	–	–	–128
		1 MHz	–	–	–145
	LCPLL0 reference clock select phase noise mask at REFCLK frequency = 312.5 MHz	10 kHz	–	–	–103	dBc/Hz
		100 kHz	–	–	–123
		1 MHz	–	–	–143
	LCPLL0 reference clock select phase noise mask at REFCLK frequency = 625 MHz	10 kHz	–	–	–98	dBc/Hz
		100 kHz	–	–	–117
		1 MHz	–	–	–140
For reference clock frequencies not in this table, use the phase-noise mask for the nearest reference clock frequency. This reference clock phase-noise mask is superseded by any reference clock phase-noise mask that is specified in a supported protocol.

Table 5. GTM Transceiver PLL/Lock Time Adaptation
Symbol	Description	Conditions		All Speed Grades			Units
Symbol	Description	Conditions		Min	Typ	Max	Units
T_LOCK	Initial PLL lock	53.125 Gb/s line rate with 156.25 MHz REFCLK		–	–	3	ms
T_LOCK	Initial PLL lock	All other cases		–	–	5.7	ms
T_DLOCK	Clock recovery phase acquisition and adaptation time	PAM4 (<39 Gb/s)	Short reach (IL < 12db)	–	5.90×10¹⁰	–	UI
		PAM4 (<39 Gb/s)	Long reach (IL ≥ 12db)	–	3.05×10⁹	–	UI
		PAM4 (≥39 Gb/s)	Short reach (IL < 12db)	–	3.67×10¹⁰	–	UI
		PAM4 (≥39 Gb/s)	Long reach (IL ≥ 12db)	–	6.09×10⁹	–	UI
		NRZ		–	6.09×10⁹	–	UI

Table 6. GTM Transceiver User Clock Switching Characteristics
Symbol	Description¹		Data Width Conditions (Bit)		Speed Grade and V_CCINT Operating Voltages				Units
			Data Width Conditions (Bit)		0.90V	0.85V		0.72V
			Internal Logic	Interconnect Logic	-3	-2	-1	-2
F_TXOUTPMA	TXOUTCLK maximum frequency sourced from OUTCLKPMA				453.13	440.78	415.63	440.78	MHz
F_RXOUTPMA	RXOUTCLK maximum frequency sourced from OUTCLKPMA				453.13	440.78	415.63	440.78	MHz
F_TXOUTPROGDIV	TXOUTCLK maximum frequency sourced from TXPROGDIVCLK				725.00	705.25	665.00	705.25	MHz
F_RXOUTPROGDIV	RXOUTCLK maximum frequency sourced from RXPROGDIVCLK				725.00	705.25	665.00	705.25	MHz
F_TXIN	TXUSRCLK maximum frequency	PAM4	80	80	725.00	705.25	665.00	705.25	MHz
			128	128	453.13	440.78	415.63	440.78	MHz
			80	160	725.00	705.25	665.00	705.25	MHz
			128	256	453.13	440.78	415.63	440.78	MHz
		NRZ	64	64	453.13	440.78	415.63	440.78	MHz
		NRZ	64	128	453.13	440.78	415.63	440.78	MHz
F_RXIN	RXUSRCLK maximum frequency	PAM4	80	80	725.00	705.25	665.00	705.25	MHz
			128	128	453.13	440.78	415.63	440.78	MHz
			80	160	725.00	705.25	665.00	705.25	MHz
			128	256	453.13	440.78	415.63	440.78	MHz
		NRZ	64	64	453.13	440.78	415.63	440.78	MHz
		NRZ	64	128	453.13	440.78	415.63	440.78	MHz
F_TXIN2	TXUSRCLK2 maximum frequency	PAM4	80	80	725.00	705.25	665.00	705.25	MHz
			128	128	453.13	440.78	415.63	440.78	MHz
			80	160	362.50	352.63	332.50	352.63	MHz
			128	256	226.56	220.39	207.81	220.39	MHz
		NRZ	64	64	453.13	440.78	415.63	440.78	MHz
		NRZ	64	128	226.56	220.39	207.81	220.39	MHz
F_RXIN2	RXUSRCLK2 maximum frequency	PAM4	80	80	725.00	705.25	665.00	705.25	MHz
			128	128	453.13	440.78	415.63	440.78	MHz
			80	160	362.50	352.63	332.50	352.63	MHz
			128	256	226.56	220.39	207.81	220.39	MHz
		NRZ	64	64	453.13	440.78	415.63	440.78	MHz
		NRZ	64	128	226.56	220.39	207.81	220.39	MHz
Clocking must be implemented as described in the Virtex UltraScale+ FPGAs GTM Transceivers User Guide (UG581).

Table 7. GTM Transceiver Transmitter Switching Characteristics
Symbol	Description	Conditions		Min	Typ	Max	Units
F_GTMPAMTX	Transmitter PAM4 serial data rate range			20.6	–	F_GTMPAMMAX	Gb/s
F_GTMNRZTX	Transmitter NRZ serial data rate range			10.3	–	F_GTMNRZMAX	Gb/s
T_SLEW	TX slew rate			–	4.76×10⁴	–	V/μs
T_{J4U58_PAM4}	TX uncorrelated jitter @10^–4	PAM4	58 Gb/s	–	–	0.118	UI
T_{EOJ58_PAM4}	TX even-odd jitter¹	PAM4	58 Gb/s	–	–	0.019	UI
T_{J4U56.5_PAM4}	TX uncorrelated jitter @10^–4	PAM4	56.5 Gb/s	–	–	0.118	UI
T_{EOJ56.5_PAM4}	TX even-odd jitter¹	PAM4	56.5 Gb/s	–	–	0.019	UI
T_{J4U53.125_PAM4}	TX uncorrelated jitter @10^–4	PAM4	53.125 Gb/s	–	–	0.118	UI
T_{EOJ53.125_PAM4}	TX even-odd jitter¹	PAM4	53.125 Gb/s	–	–	0.019	UI
T_{J4U48_PAM4}	TX uncorrelated jitter @10^–4	PAM4	48 Gb/s	–	–	0.118	UI
T_{EOJ48_PAM4}	TX even-odd jitter¹	PAM4	48 Gb/s	–	–	0.019	UI
T_{J4U40_PAM4}	TX uncorrelated jitter @10^–4	PAM4	40 Gb/s	–	–	0.118	UI
T_{EOJ40_PAM4}	TX even-odd jitter¹	PAM4	40 Gb/s	–	–	0.019	UI
T_{J4U28.21_PAM4}	TX uncorrelated jitter @10^–4	PAM4	28.21 Gb/s	–	–	0.118	UI
T_{EOJ28.21_PAM4}	Deterministic jitter¹	PAM4	28.21 Gb/s	–	–	0.019	UI
T_{J4U20.6_PAM4}	TX uncorrelated jitter @10^–4	PAM4	20.6 Gb/s	–	–	0.118	UI
T_{EOJ20.6_PAM4}	TX even-odd jitter¹	PAM4	20.6 Gb/s	–	–	0.019	UI
T_{J29_NRZ}	Total jitter^{1, 2}	NRZ	29 Gb/s	–	–	0.28	UI
D_{J29_NRZ}	Deterministic jitter^{1, 2}	NRZ	29 Gb/s	–	–	0.17	UI
T_{J28.21_NRZ}	Total jitter^{1, 2}	NRZ	28.21 Gb/s	–	–	0.28	UI
D_{J28.21_NRZ}	Deterministic jitter^{1, 2}	NRZ	28.21 Gb/s	–	–	0.17	UI
T_{J26.5625_NRZ}	Total jitter^{1, 2}	NRZ	26.5625 Gb/s	–	–	0.28	UI
D_{J26.5625_NRZ}	Deterministic jitter^{1, 2}	NRZ	26.5625 Gb/s	–	–	0.17	UI
T_{J25.78125_NRZ}	Total jitter^{1, 2}	NRZ	25.78125 Gb/s	–	–	0.28	UI
D_{J25.78125_NRZ}	Deterministic jitter^{1, 2}	NRZ	25.78125 Gb/s	–	–	0.17	UI
T_{J24_NRZ}	Total jitter^{1, 2}	NRZ	24 Gb/s	–	–	0.28	UI
D_{J24_NRZ}	Deterministic jitter^{1, 2}	NRZ	24 Gb/s	–	–	0.17	UI
T_{J19.6_NRZ}	Total jitter^{1, 2}	NRZ	19.6 Gb/s	–	–	0.28	UI
D_{J19.6_NRZ}	Deterministic jitter^{1, 2}	NRZ	19.6 Gb/s	–	–	0.17	UI
Using LCPLL_FBDIV = 40, 80-bit internal data width. These values are NOT intended for protocol specific compliance determinations. NRZ jitter values are based on a bit-error ratio of 10^–12.

Table 8. GTM Transceiver Receiver Switching Characteristics
Symbol	Description	Conditions		Min	Typ	Max	Units
F_GTMPAMRX	Receiver PAM4 serial data rate range			20.6	–	F_GTMPAM4MAX	Gb/s
F_GTMNRZRX	Receiver NRZ serial data rate range			10.3	–	F_GTMNRZ4MAX	Gb/s
R_XRL	Run length (CID)			–	–	128	UI
R_XPPMTOL	Data/REFCLK PPM offset tolerance			–200	–	200	ppm
SJ Jitter Tolerance^{2, 3, 1}
J_{T_SJ58_PAM4}	Sinusoidal jitter	PAM4	58 Gb/s	0.07	–	–	UI
J_{T_SJ56.5_PAM4}	Sinusoidal jitter	PAM4	56.5 Gb/s	0.07	–	–	UI
J_{T_SJ53.125_PAM4}	Sinusoidal jitter	PAM4	53.125 Gb/s	0.07	–	–	UI
J_{T_SJ48_PAM4}	Sinusoidal jitter	PAM4	48 Gb/s	0.07	–	–	UI
J_{T_SJ39.2_PAM4}	Sinusoidal jitter	PAM4	39.2 Gb/s	0.07	–	–	UI
J_{T_SJ29_PAM4}	Sinusoidal jitter	PAM4	29 Gb/s	0.07	–	–	UI
J_{T_SJ20.6_PAM4}	Sinusoidal jitter	PAM4	20.6 Gb/s	0.07	–	–	UI
J_{T_SJ29_NRZ}	Sinusoidal jitter	NRZ	29 Gb/s	0.3	–	–	UI
J_{T_SJ25.78125_NRZ}	Sinusoidal jitter	NRZ	25.78125 Gb/s	0.3	–	–	UI
J_{T_SJ19.6_NRZ}	Sinusoidal jitter	NRZ	19.6 Gb/s	0.3	–	–	UI
J_{T_SJ15_NRZ}	Sinusoidal jitter	NRZ	15.0 Gb/s	0.3	–	–	UI
J_{T_SJ10.3_NRZ}	Sinusoidal jitter	NRZ	10.3 Gb/s	0.3	–	–	UI
PAM4 values are measured at a bit error ratio of 10^–6. NRZ values are based on a bit error ratio of 10^–12. The frequency of the injected sinusoidal jitter is 10 MHz.

GTM Transceiver Switching Characteristics - DS923

Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923)