GTM Transceiver Switching Characteristics

Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923)
Document ID
DS923
Release Date
2024-08-09
Revision
1.20 English

Consult the Virtex UltraScale+ FPGAs GTM Transceivers User Guide (UG581) for further information.

Table 1. GTM Transceiver Performance
Symbol Description 1, 2 Output Divider Speed Grade and VCCINT Operating Voltages Units
0.90V 0.85V 0.72V
-3 -2 -1 -2
Max Max Max Max
FGTMPAM4MAX GTM transceiver PAM4 maximum line rate 1 58.00 56.42 53.20 56.42 Gb/s
FGTMPAM4MIN GTM transceiver PAM4 minimum line rate 39.20 39.20 39.20 39.20 Gb/s
FGTMPAM42MAX GTM transceiver PAM4 maximum line rate 2 29.00 28.21 26.60 28.21 Gb/s
FGTMPAM42MIN GTM transceiver PAM4 minimum line rate 20.60 20.60 20.60 20.60 Gb/s
FGTMNRZMAX GTM transceiver NRZ maximum line rate 1 29.00 28.21 26.60 28.21 Gb/s
FGTMNRZMIN GTM transceiver NRZ minimum line rate 19.60 19.60 19.60 19.60 Gb/s
FGTMNRZ2MAX GTM transceiver NRZ maximum line rate 2 14.50 14.105 13.30 14.105 Gb/s
FGTMNRZ2MIN GTM transceiver NRZ minimum line rate 10.30 10.30 10.30 10.30 Gb/s
  1. For PAM4, data rates from FGTMPAM42MAX to 39.2 Gb/s are not available.
  2. For NRZ, data rates from FGTMNRZ2MAX to 19.6 Gb/s are not available.
Table 2. GTM Transceiver Dynamic Reconfiguration Port (DRP) Switching Characteristics
Symbol Description All Speed Grades Units
FGTMDRPCLK GTMDRPCLK maximum frequency 250 MHz
Table 3. GTM Transceiver Reference Clock Switching Characteristics
Symbol Description Conditions All Speed Grades Units
Min Typ Max
FGCLK Reference clock frequency range 60 – 820 MHz
TRCLK Reference clock rise time 20% – 80% – 200 – ps
TFCLK Reference clock fall time 80% – 20% – 200 – ps
TDCREF Reference clock duty cycle Transceiver PLL only 40 50 60 %
Table 4. GTM Transceiver Reference Clock Oscillator Selection Phase Noise Mask
Symbol Description 1, 2 Offset Frequency Min Typ Max Units
LCPLLREFCLKMASK LCPLL reference clock select phase noise mask at REFCLK frequency = 156.25 MHz 10 kHz – – –112 dBc/Hz
100 kHz – – –128
1 MHz – – –145
LCPLL0 reference clock select phase noise mask at REFCLK frequency = 312.5 MHz 10 kHz – – –103 dBc/Hz
100 kHz – – –123
1 MHz – – –143
LCPLL0 reference clock select phase noise mask at REFCLK frequency = 625 MHz 10 kHz – – –98 dBc/Hz
100 kHz – – –117
1 MHz – – –140
  1. For reference clock frequencies not in this table, use the phase-noise mask for the nearest reference clock frequency.
  2. This reference clock phase-noise mask is superseded by any reference clock phase-noise mask that is specified in a supported protocol.
Table 5. GTM Transceiver PLL/Lock Time Adaptation
Symbol Description Conditions All Speed Grades Units
Min Typ Max
TLOCK Initial PLL lock 53.125 Gb/s line rate with 156.25 MHz REFCLK – – 3 ms
All other cases – – 5.7 ms
TDLOCK Clock recovery phase acquisition and adaptation time PAM4 (<39 Gb/s) Short reach (IL < 12db) – 5.90×1010 – UI
Long reach (IL ≥ 12db) – 3.05×109 – UI
PAM4 (≥39 Gb/s) Short reach (IL < 12db) – 3.67×1010 – UI
Long reach (IL ≥ 12db) – 6.09×109 – UI
NRZ – 6.09×109 – UI
Table 6. GTM Transceiver User Clock Switching Characteristics
Symbol Description 1 Data Width Conditions (Bit) Speed Grade and VCCINT Operating Voltages Units
0.90V 0.85V 0.72V
Internal Logic Interconnect Logic -3 -2 -1 -2
FTXOUTPMA TXOUTCLK maximum frequency sourced from OUTCLKPMA 453.13 440.78 415.63 440.78 MHz
FRXOUTPMA RXOUTCLK maximum frequency sourced from OUTCLKPMA 453.13 440.78 415.63 440.78 MHz
FTXOUTPROGDIV TXOUTCLK maximum frequency sourced from TXPROGDIVCLK 725.00 705.25 665.00 705.25 MHz
FRXOUTPROGDIV RXOUTCLK maximum frequency sourced from RXPROGDIVCLK 725.00 705.25 665.00 705.25 MHz
FTXIN TXUSRCLK maximum frequency PAM4 80 80 725.00 705.25 665.00 705.25 MHz
128 128 453.13 440.78 415.63 440.78 MHz
80 160 725.00 705.25 665.00 705.25 MHz
128 256 453.13 440.78 415.63 440.78 MHz
NRZ 64 64 453.13 440.78 415.63 440.78 MHz
64 128 453.13 440.78 415.63 440.78 MHz
FRXIN RXUSRCLK maximum frequency PAM4 80 80 725.00 705.25 665.00 705.25 MHz
128 128 453.13 440.78 415.63 440.78 MHz
80 160 725.00 705.25 665.00 705.25 MHz
128 256 453.13 440.78 415.63 440.78 MHz
NRZ 64 64 453.13 440.78 415.63 440.78 MHz
64 128 453.13 440.78 415.63 440.78 MHz
FTXIN2 TXUSRCLK2 maximum frequency PAM4 80 80 725.00 705.25 665.00 705.25 MHz
128 128 453.13 440.78 415.63 440.78 MHz
80 160 362.50 352.63 332.50 352.63 MHz
128 256 226.56 220.39 207.81 220.39 MHz
NRZ 64 64 453.13 440.78 415.63 440.78 MHz
64 128 226.56 220.39 207.81 220.39 MHz
FRXIN2 RXUSRCLK2 maximum frequency PAM4 80 80 725.00 705.25 665.00 705.25 MHz
128 128 453.13 440.78 415.63 440.78 MHz
80 160 362.50 352.63 332.50 352.63 MHz
128 256 226.56 220.39 207.81 220.39 MHz
NRZ 64 64 453.13 440.78 415.63 440.78 MHz
64 128 226.56 220.39 207.81 220.39 MHz
  1. Clocking must be implemented as described in the Virtex UltraScale+ FPGAs GTM Transceivers User Guide (UG581).
Table 7. GTM Transceiver Transmitter Switching Characteristics
Symbol Description Conditions Min Typ Max Units
FGTMPAMTX Transmitter PAM4 serial data rate range 20.6 – FGTMPAMMAX Gb/s
FGTMNRZTX Transmitter NRZ serial data rate range 10.3 – FGTMNRZMAX Gb/s
TSLEW TX slew rate – 4.76×104 – V/μs
TJ4U58_PAM4 TX uncorrelated jitter @10–4 PAM4 58 Gb/s – – 0.118 UI
TEOJ58_PAM4 TX even-odd jitter 1 – – 0.019 UI
TJ4U56.5_PAM4 TX uncorrelated jitter @10–4 PAM4 56.5 Gb/s – – 0.118 UI
TEOJ56.5_PAM4 TX even-odd jitter 1 – – 0.019 UI
TJ4U53.125_PAM4 TX uncorrelated jitter @10–4 PAM4 53.125 Gb/s – – 0.118 UI
TEOJ53.125_PAM4 TX even-odd jitter 1 – – 0.019 UI
TJ4U48_PAM4 TX uncorrelated jitter @10–4 PAM4 48 Gb/s – – 0.118 UI
TEOJ48_PAM4 TX even-odd jitter 1 – – 0.019 UI
TJ4U40_PAM4 TX uncorrelated jitter @10–4 PAM4 40 Gb/s – – 0.118 UI
TEOJ40_PAM4 TX even-odd jitter 1 – – 0.019 UI
TJ4U28.21_PAM4 TX uncorrelated jitter @10–4 PAM4 28.21 Gb/s – – 0.118 UI
TEOJ28.21_PAM4 Deterministic jitter 1 – – 0.019 UI
TJ4U20.6_PAM4 TX uncorrelated jitter @10–4 PAM4 20.6 Gb/s – – 0.118 UI
TEOJ20.6_PAM4 TX even-odd jitter 1 – – 0.019 UI
TJ29_NRZ Total jitter 1, 2 NRZ 29 Gb/s – – 0.28 UI
DJ29_NRZ Deterministic jitter 1, 2 – – 0.17 UI
TJ28.21_NRZ Total jitter 1, 2 NRZ 28.21 Gb/s – – 0.28 UI
DJ28.21_NRZ Deterministic jitter 1, 2 – – 0.17 UI
TJ26.5625_NRZ Total jitter 1, 2 NRZ 26.5625 Gb/s – – 0.28 UI
DJ26.5625_NRZ Deterministic jitter 1, 2 – – 0.17 UI
TJ25.78125_NRZ Total jitter 1, 2 NRZ 25.78125 Gb/s – – 0.28 UI
DJ25.78125_NRZ Deterministic jitter 1, 2 – – 0.17 UI
TJ24_NRZ Total jitter 1, 2 NRZ 24 Gb/s – – 0.28 UI
DJ24_NRZ Deterministic jitter 1, 2 – – 0.17 UI
TJ19.6_NRZ Total jitter 1, 2 NRZ 19.6 Gb/s – – 0.28 UI
DJ19.6_NRZ Deterministic jitter 1, 2 – – 0.17 UI
  1. Using LCPLL_FBDIV = 40, 80-bit internal data width. These values are NOT intended for protocol specific compliance determinations.
  2. NRZ jitter values are based on a bit-error ratio of 10–12.
Table 8. GTM Transceiver Receiver Switching Characteristics
Symbol Description Conditions Min Typ Max Units
FGTMPAMRX Receiver PAM4 serial data rate range 20.6 – FGTMPAM4MAX Gb/s
FGTMNRZRX Receiver NRZ serial data rate range 10.3 – FGTMNRZ4MAX Gb/s
RXRL Run length (CID) – – 128 UI
RXPPMTOL Data/REFCLK PPM offset tolerance –200 – 200 ppm
SJ Jitter Tolerance 2, 3, 1
JT_SJ58_PAM4 Sinusoidal jitter PAM4 58 Gb/s 0.07 – – UI
JT_SJ56.5_PAM4 Sinusoidal jitter PAM4 56.5 Gb/s 0.07 – – UI
JT_SJ53.125_PAM4 Sinusoidal jitter PAM4 53.125 Gb/s 0.07 – – UI
JT_SJ48_PAM4 Sinusoidal jitter PAM4 48 Gb/s 0.07 – – UI
JT_SJ39.2_PAM4 Sinusoidal jitter PAM4 39.2 Gb/s 0.07 – – UI
JT_SJ29_PAM4 Sinusoidal jitter PAM4 29 Gb/s 0.07 – – UI
JT_SJ20.6_PAM4 Sinusoidal jitter PAM4 20.6 Gb/s 0.07 – – UI
JT_SJ29_NRZ Sinusoidal jitter NRZ 29 Gb/s 0.3 – – UI
JT_SJ25.78125_NRZ Sinusoidal jitter NRZ 25.78125 Gb/s 0.3 – – UI
JT_SJ19.6_NRZ Sinusoidal jitter NRZ 19.6 Gb/s 0.3 – – UI
JT_SJ15_NRZ Sinusoidal jitter NRZ 15.0 Gb/s 0.3 – – UI
JT_SJ10.3_NRZ Sinusoidal jitter NRZ 10.3 Gb/s 0.3 – – UI
  1. PAM4 values are measured at a bit error ratio of 10–6.
  2. NRZ values are based on a bit error ratio of 10–12.
  3. The frequency of the injected sinusoidal jitter is 10 MHz.