Device Pin-to-Pin Input Parameter Guidelines

Virtex UltraScale+ FPGA Data Sheet: DC and AC Switching Characteristics (DS923)
Document ID
DS923
Release Date
2024-08-09
Revision
1.20 English

The pin-to-pin numbers in the following table are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.

Table 1. Global Clock Input Setup and Hold With 3.3V HD I/O Without MMCM
Symbol Description Device Speed Grade and VCCINT Operating Voltages Units
0.90V 0.85V 0.72V
-3 -2 -1 -2
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard. 1, 2, 3
TPSFD_VU19P Global clock input and input flip-flop (or latch) without MMCM Setup XCVU19P N/A –0.09 –0.14 N/A ns
TPHFD_VU19P Hold N/A 1.54 1.68 N/A ns
TPSFD_VU23P Setup XCVU23P 0.88 1.03 1.04 1.99 ns
TPHFD_VU23P Hold 0.51 0.51 0.51 0.51 ns
  1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
  2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.
  3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 2. Global Clock Input Setup and Hold With MMCM
Symbol Description Device Speed Grade and VCCINT Operating Voltages Units
0.90V 0.85V 0.72V
-3 -2 -1 -2
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard. 1, 2, 3
TPSMMCMCC_VU3P Global clock input and input flip-flop (or latch) with MMCM Setup XCVU3P 1.86 1.86 1.99 1.86 ns
TPHMMCMCC_VU3P Hold –0.13 –0.13 –0.13 –0.17 ns
TPSMMCMCC_VU5P Setup XCVU5P 1.86 1.86 1.99 1.86 ns
TPHMMCMCC_VU5P Hold –0.13 –0.13 –0.13 –0.17 ns
TPSMMCMCC_VU7P Setup XCVU7P 1.86 1.86 1.99 1.86 ns
TPHMMCMCC_VU7P Hold –0.13 –0.13 –0.13 –0.17 ns
TPSMMCMCC_VU9P Setup XCVU9P 1.86 1.86 1.99 1.86 ns
TPHMMCMCC_VU9P Hold –0.13 –0.13 –0.13 –0.17 ns
TPSMMCMCC_VU11P Setup XCVU11P 1.91 1.92 2.05 1.92 ns
TPHMMCMCC_VU11P Hold –0.13 –0.13 –0.13 –0.18 ns
TPSMMCMCC_VU13P Setup XCVU13P 1.91 1.92 2.05 1.92 ns
TPHMMCMCC_VU13P Hold –0.13 –0.13 –0.13 –0.18 ns
TPSMMCMCC_VU19P Setup XCVU19P N/A 1.99 2.13 N/A ns
TPHMMCMCC_VU19P Hold N/A –0.08 –0.08 N/A ns
TPSMMCMCC_VU23P Setup XCVU23P 2.07 2.08 2.22 2.08 ns
TPHMMCMCC_VU23P Hold –0.10 –0.10 –0.10 –0.10 ns
TPSMMCMCC_VU27P Setup XCVU27P 1.91 1.92 2.05 1.92 ns
TPHMMCMCC_VU27P Hold –0.13 –0.13 –0.13 –0.18 ns
TPSMMCMCC_VU29P Setup XCVU29P 1.91 1.92 2.05 1.92 ns
TPHMMCMCC_VU29P Hold –0.13 –0.13 –0.13 –0.18 ns
TPSMMCMCC_VU31P Setup XCVU31P 1.91 1.92 2.05 1.92 ns
TPHMMCMCC_VU31P Hold –0.13 –0.13 –0.13 –0.18 ns
TPSMMCMCC_VU33P Setup XCVU33P 1.91 1.92 2.05 1.92 ns
TPHMMCMCC_VU33P Hold –0.13 –0.13 –0.13 –0.18 ns
TPSMMCMCC_VU35P Setup XCVU35P 1.91 1.92 2.05 1.92 ns
TPHMMCMCC_VU35P Hold –0.13 –0.13 –0.13 –0.18 ns
TPSMMCMCC_VU37P Setup XCVU37P 1.91 1.92 2.05 1.92 ns
TPHMMCMCC_VU37P Hold –0.13 –0.13 –0.13 –0.18 ns
TPSMMCMCC_VU45P Global clock input and input flip-flop (or latch) with MMCM (cont'd) Setup XCVU45P 1.91 1.92 2.05 1.92 ns
TPHMMCMCC_VU45P Hold –0.13 –0.13 –0.13 –0.18 ns
TPSMMCMCC_VU47P Setup XCVU47P 1.91 1.92 2.05 1.92 ns
TPHMMCMCC_VU47P Hold –0.13 –0.13 –0.13 –0.18 ns
TPSMMCMCC_VU57P Setup XCVU57P 1.91 1.92 2.05 1.92 ns
TPHMMCMCC_VU57P Hold –0.15 –0.13 –0.13 –0.18 ns
TPSMMCMCC_XQVU3P Setup XQVU3P N/A 1.86 1.99 1.86 ns
TPHMMCMCC_XQVU3P Hold N/A –0.13 –0.13 –0.17 ns
TPSMMCMCC_XQVU7P Setup XQVU7P N/A 1.86 1.99 1.86 ns
TPHMMCMCC_XQVU7P Hold N/A –0.13 –0.13 –0.17 ns
TPSMMCMCC_XQVU11P Setup XQVU11P N/A 1.92 2.05 1.92 ns
TPHMMCMCC_XQVU11P Hold N/A –0.13 –0.13 –0.18 ns
  1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
  2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net in a single SLR.
  3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 3. Sampling Window
Description Speed Grade and VCCINT Operating Voltages Units
0.90V 0.85V 0.72V
-3 -2 -1 -2
TSAMP_BUFG 1 510 610 610 610 ps
TSAMP_NATIVE_DPA 2 100 100 125 125 ps
TSAMP_NATIVE_BISC 3 60 60 85 85 ps
  1. This parameter indicates the total sampling error of the Virtex UltraScale+ FPGA DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers' edges of operation. These measurements include: CLK0 MMCM jitter, MMCM accuracy (phase offset), and MMCM phase shift resolution. These measurements do not include package or clock tree skew.
  2. This parameter is the receive sampling error for RX_BITSLICE when using dynamic phase alignment.
  3. This parameter is the receive sampling error for RX_BITSLICE when using built-in self-calibration (BISC).
Table 4. Input Logic Characteristics for Dynamic Phase Aligned Applications (Component Mode)
Description Speed Grade and VCCINT Operating Voltages Units
0.90V 0.85V 0.72V
-3 -2 -1 -2
TINPUT_LOGIC_UNCERTAINTY 1 40 ps
TCAL_ERROR 2 24 ps
  1. Input_logic_uncertainty accounts for the setup/hold and any pattern dependent jitter for the input logic (input register, IDDRE1, or ISERDESE3).
  2. Calibration error associated with quantization effects based on the IDELAY resolution. Calibration must be performed for each input pin to ensure optimal performance.