Revision History

Added note about V_IN for POR_OVERRIDE pin to Table 1 and Table 1.

For clarity, moved the location of the specifications for internal V_REF, differential termination, and temperature diode (ideality factor and series resistance) in Table 1.

In Table 1, updated notes 1 and 4, and expanded V_CCO table note into notes 5 and 6.

Updated note 7 in Table 2.

Updated note 8 and note 10 in Table 4.

Revised the Production Specification speed file version for XCKU19P in Table 1 to Vivado Design Suite from 2020.2.2 v1.32 to 2022.1 v1.34.

Updated MIPI D-PHY data rate per lane for XQ devices in -3 and -2 (0.72V) speed grades in Table 3.

Updated to PCIe Gen1, 2, 3, 4 protocol in Table 1 and Table 1.

Added notes 1 and 2 to Table 1.

Revised some of the XCKU19P speed files in Table 1, Table 2, Table 3, Table 1, and Table 2.

For the KU19P device only, added PCIE4C support in Table 2.

Added the XCKU19P device to Table 1, Table 1, and Table 1 in Vivado Design Suite 2020.2 v1.04, and where applicable in other sections of this data sheet.

Added Note 10 to Table 4.

Increased the maximum line rate of the QPLL0 -1 (V_CCINT = 0.85V) output divider 1 in Table 1 and updated Notes 3 and 4.

Added Note 4 to the Configuration Switching Characteristics table.

Added LVDS component mode notes to FPGA Logic Performance Characteristics.

Removed PCI Express Gen4 support in Integrated Interface Block for PCI Express Designs and Note 1, Note 2, and Note 3.

In Table 2, added Note 4 to the LVDS RX DDR maximum data.

In Table 1, revised the calculated values from 322.223 to 322.266.

Revised the speed grade -1 (V_CCINT = 0.85) F_GTYMAX in Table 1, which also revised values in Table 6 and added Note 6.

Updated Table 1, Table 1, and Table 1 to production release the XCKU3P, XCKU5P, XCKU11P, XCKU13P, and XCKU15P devices in the -3E speed/temperature grade in Vivado Design Suite 2018.1 v1.19.

Added Table 4 and Table 4. Added Note 2 and 3 to Table 3.

Revised Table 1 to add specific mode specifications and remove Notes 1 and 2.

Updated Table 1, Table 1, and Table 1 to production release the XCKU11P with -2LE and -1LI speed/temperature grades in Vivado Design Suite 2017.4.1.

Revised some of the -3E and -1LI/-2LE (V_CCINT = 0.72V) speed files in Table 1, Table 1, Table 2, Table 3, Table 1, and Table 2.

Updated Table 1, Table 1, and Table 1 to production release the following devices/speed/temperature grades in Vivado Design Suite 2017.4.

XCKU3P: -2LE, -1LI

XCKU5P: -2LE, -1LI

Revised the F_REFCLK descriptions in Table 1. Revised the F_GTYQRANGE2 -1 speed grade minimum in Table 1. Added T_SPICCM2 and T_SPICCFC2 to Table 1.

In Table 1, corrected the minimum voltage for the System Monitor section.

Updated Table 1, Table 1, and Table 1 to production release the following devices/speed/temperature grades in Vivado Design Suite 2017.3.1.

XCKU9P: -2LE, -1LI

XCKU13P: -2LE, -1LI

Updated speed file data for this release in Table 1, Table 2, Table 3, and Table 1. Updated the notes for F_GTYMAX in Table 1.

In Table 1, because the voltages are covered in Table 1, removed the note on V_IN for I/O input voltage for HD I/O banks. Updated T_SOL by package in Table 1. Added Note 2 to Table 1.

Updated Table 1, Table 1, and Table 1 the XCKU11P: -2E, -2I, -1E, -1I (all V_CCINT = 0.85V) to production in Vivado Design Suite 2017.3 v1.14. Also updated speed file data for this release in Table 1, Table 2, Table 3, Table 1, and Table 2.

Updated Table 1, Table 1, and Table 1 to production release the following devices/speed/temperature grades in Vivado Design Suite 2017.2.1.

XCKU15P: -2E, -2I, -1E, -1I (all V_CCINT = 0.85V)

In Table 1, revised the T_{OUTBUF_DELAY_O_PAD} -2 (V_CCINT = 0.85V) values for DIFF_SSTL135_S, DIFF_SSTL15_DCI_S, DIFF_SSTL15_S, DIFF_SSTL18_I_DCI_S, and DIFF_SSTL18_I_S.

Revised some of the -3E and -1LI/-2LE (V_CCINT = 0.72V) speed files in Table 1, Table 1, Table 1, Table 1, Table 2, Table 3, Table 1, and Table 2.

Updated Table 1, Table 1, and Table 1 to production release the following devices/speed/temperature grades in Vivado Design Suite 2017.2.

XCKU13P: -2E, -2I, -1E, -1I (all V_CCINT = 0.85V)

Updated Note 11 in Table 1 for clarity. Revised the -3E and -1LI/-2LE (V_CCINT = 0.72V) speed files in Table 1, Table 1, Table 1, Table 1, Table 2, Table 3, Table 1, and Table 2. Updated the F_MAX symbol names and values in Table 1. Added Note 1 to Table 1. Added Note 3 to Table 1.

Updated Table 1 and Table 1 to production release the following devices/speed/temperature grades in Vivado Design Suite 2017.1.

XCKU9P: -2E, -2I, -1E, -1I

Removed the MIPI_DPHY_DCI_LP standard from Table 1 (HD I/O banks never supported DCI). Revised the minimum 32.75 Gb/s sinusoidal jitter in Table 8.

Updated the Summary description. In Table 1, updated and added data, and updated Note 6, added Note 7, Note 8, and Note 9. Updated and added data to Table 1, revised Note 11 and added Note 12 and Note 13. Updated Table 1 and added Note 6. Added specifications to Table 1 though Table 1. Updated maximum V_ICM and Note 1 in Table 1. Updated the maximum V_ODIFF in Table 1.

Updated Table 1, Table 1, and Table 1 to production release the following devices/speed/temperature grades in Vivado Design Suite 2017.1.

XCKU3P: -2E, -2I, -1E, -1I

XCKU5P: -2E, -2I, -1E, -1I

Added Note 1 to Table 1. Updated Table 1. Updated Table 2 and added Note 2. Added Table 3. Updated Table 5 and added Note 3. Many revisions to the speed specifications in Table 1, Table 1, Table 1, Table 1, Table 1, Table 1, Table 1, Table 2, Table 3, Table 1, Table 2, and Table 3. Updated V_L and V_H values in Table 1. In Table 1, added T_{MINPER_CLK} and Note 1, and revised F_REFCLK. Added MMCM_F_{DPRCLK_MAX} to Table 1 and PLL_F_{DPRCLK_MAX} to Table 1. Updated Table 1. Revised the GTH Transceiver Specifications and GTY Transceiver Specifications sections. Revised the Integrated Interface Block for Interlaken and Integrated Interface Block for 100G Ethernet MAC and PCS sections. Updated the System Monitor Specifications section including On-Chip Sensor Accuracy and adding Note 3 to Table 1. Removed timing diagrams from the SYSMON I2C/PMBus Interfaces section. Updated the Configuration Switching Characteristics section. Removed the eFUSE Programming Conditions table and added the specifications to Table 1 and Table 1. Updated Table 1. Updated the Automotive Applications Disclaimer.

In Table 1 revised V_IN for HP I/O banks. Updated Note 5 in Table 1. Added values to Table 1. Added MIPI_DPHY_DCI to Table 1, Table 2, and Table 4. Updated and added notes in Table 1 and Table 1. Updated Table 1 speed specifications for Vivado Design Suite 2016.1. Removed Table 23, Video Codec Unit Performance. Updated Table 2. Expanded and updated Table 5. Updated Table 1 and Table 1. Updated Table 1 and Table 1 with MIPI D-PHY values. Updated Table 1 and Table 1. In Table 1, added the Block RAM and FIFO Clock-to-Out Delays section. Updated Table 1 to Table 2. Revised the symbol names in Table 1. Revised typical values in Table 2. Updated the -2 (0.72V) and -1 (0.72V) values in Table 1. Added Table 4 and Table 4. Added Note 2 to Table 1. Revised Table 6. Revised data and added notes to Table 1, Table 1, and Table 1. Revised INL in Table 1. Added notes to Table 1 and Table 2. Many revised sections in Table 1.