The pin-to-pin numbers in the following tables are based on the clock root
placement in the center of the device. The actual pin-to-pin values will vary if the root
placement selected is different. Consult the Vivado Design Suite timing
report for the actual pin-to-pin values.
Table 1. Global Clock Input to Output Delay Without MMCM (Near Clock Region)
| Symbol |
Description
1
|
Device |
Speed Grade and VCCINT Operating Voltages |
Units |
| 0.90V |
0.85V |
0.72V |
| -3 |
-2 |
-1 |
-2 |
-1 |
| SSTL15 Global Clock Input to Output
Delay using Output Flip-Flop, Fast Slew Rate, without MMCM |
| TICKOF
|
Global clock input and output flip-flop without MMCM (near clock region) |
XCKU3P |
4.65 |
5.09 |
5.48 |
6.37 |
6.84 |
ns |
| XCKU5P |
4.65 |
5.09 |
5.48 |
6.37 |
6.84 |
ns |
| XCKU9P |
5.42 |
5.91 |
6.35 |
7.48 |
8.03 |
ns |
| XCKU11P |
5.92 |
6.49 |
6.96 |
8.16 |
8.91 |
ns |
| XCKU13P |
5.58 |
6.09 |
6.55 |
7.75 |
8.33 |
ns |
| XCKU15P |
6.29 |
6.90 |
7.40 |
8.68 |
9.32 |
ns |
| XCKU19P |
5.85 |
6.43 |
6.91 |
8.09 |
8.72 |
ns |
| XQKU5P |
N/A |
5.09 |
5.48 |
N/A |
6.84 |
ns |
| XQKU15P |
N/A |
6.90 |
7.40 |
N/A |
9.32 |
ns |
- This table lists representative values where one
global clock input drives one vertical clock line in each accessible column, and
where all accessible I/O and CLB flip-flops are clocked by the global clock
net.
|
Table 2. Global Clock Input to Output Delay Without MMCM (Far Clock Region)
| Symbol |
Description
1
|
Device |
Speed Grade and VCCINT Operating Voltages |
Units |
| 0.90V |
0.85V |
0.72V |
| -3 |
-2 |
-1 |
-2 |
-1 |
| SSTL15 Global Clock Input to Output
Delay using Output Flip-Flop, Fast Slew Rate, without MMCM |
| TICKOF_FAR
|
Global clock input and output flip-flop without MMCM (far clock region) |
XCKU3P |
4.84 |
5.30 |
5.70 |
6.64 |
7.14 |
ns |
| XCKU5P |
4.84 |
5.30 |
5.70 |
6.64 |
7.14 |
ns |
| XCKU9P |
5.91 |
6.49 |
6.97 |
8.16 |
8.76 |
ns |
| XCKU11P |
6.29 |
6.91 |
7.41 |
8.72 |
9.52 |
ns |
| XCKU13P |
5.90 |
6.49 |
6.96 |
8.16 |
8.77 |
ns |
| XCKU15P |
6.84 |
7.53 |
8.07 |
9.52 |
10.23 |
ns |
| XCKU19P |
6.23 |
6.86 |
7.35 |
8.65 |
9.33 |
ns |
| XQKU5P |
N/A |
5.30 |
5.70 |
N/A |
7.14 |
ns |
| XQKU15P |
N/A |
7.53 |
8.07 |
N/A |
10.23 |
ns |
- This table lists representative values where
one global clock input drives one vertical clock line in each accessible column,
and where all accessible I/O and CLB flip-flops are clocked by the global clock
net.
|
Table 3. Global Clock Input to Output Delay With MMCM
| Symbol |
Description
1, 2
|
Device |
Speed Grade and VCCINT Operating Voltages |
Units |
| 0.90V |
0.85V |
0.72V |
| -3 |
-2 |
-1 |
-2 |
-1 |
| SSTL15 Global Clock Input to Output
Delay using Output Flip-Flop, Fast Slew Rate, with MMCM |
| TICKOFMMCMCC
|
Global clock input and output flip-flop with MMCM |
XCKU3P |
1.67 |
1.98 |
2.17 |
2.59 |
2.74 |
ns |
| XCKU5P |
1.67 |
1.98 |
2.17 |
2.59 |
2.74 |
ns |
| XCKU9P |
1.83 |
2.15 |
2.36 |
2.80 |
2.95 |
ns |
| XCKU11P |
1.96 |
2.30 |
2.51 |
2.99 |
3.20 |
ns |
| XCKU13P |
1.85 |
2.18 |
2.38 |
2.82 |
2.98 |
ns |
| XCKU15P |
2.08 |
2.44 |
2.66 |
3.15 |
3.33 |
ns |
| XCKU19P |
1.82 |
2.18 |
2.39 |
2.86 |
3.04 |
ns |
| XQKU5P |
N/A |
1.98 |
2.17 |
N/A |
2.74 |
ns |
| XQKU15P |
N/A |
2.44 |
2.66 |
N/A |
3.33 |
ns |
- This table lists representative values
where one global clock input drives one vertical clock line in each accessible
column, and where all accessible I/O and CLB flip-flops are clocked by the global
clock net.
- MMCM output jitter is already included in
the timing calculation.
|
Table 4. Source Synchronous Output Characteristics (Component Mode)
| Description |
Speed Grade and VCCINT
Operating Voltages |
Units |
| 0.90V |
0.85V |
0.72V |
| -3 |
-2 |
-1 |
-2 |
-1 |
| TOUTPUT_LOGIC_DELAY_VARIATION
1
|
80 |
ps |
- Delay mismatch across a transmit bus when using
component mode output logic (ODDRE1, OSERDESE3) within a bank.
|