Device Pin-to-Pin Input Parameter Guidelines

Kintex UltraScale+ FPGAs Data Sheet: DC and AC Switching Characteristics (DS922)
Document ID
DS922
Release Date
2024-08-09
Revision
1.18 English

The pin-to-pin numbers in the following tables are based on the clock root placement in the center of the device. The actual pin-to-pin values will vary if the root placement selected is different. Consult the Vivado Design Suite timing report for the actual pin-to-pin values.

Table 1. Global Clock Input Setup and Hold With 3.3V HD I/O Without MMCM
Symbol Description Device Speed Grade and VCCINT Operating Voltages Units
0.90V 0.85V 0.72V
-3 -2 -1 -2 -1
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard. 1, 2, 3
TPSFD_KU3P Global clock input and input flip-flop (or latch) without MMCM Setup XCKU3P 1.98 2.28 2.38 3.55 3.83 ns
TPHFD_KU3P Hold –0.36 –0.36 –0.36 –1.04 –1.04 ns
TPSFD_KU5P Setup XCKU5P 1.98 2.28 2.38 3.55 3.83 ns
TPHFD_KU5P Hold –0.36 –0.36 –0.36 –1.04 –1.04 ns
TPSFD_KU9P Setup XCKU9P 1.51 1.79 1.86 2.85 3.06 ns
TPHFD_KU9P Hold –0.05 –0.05 –0.05 –0.60 –0.60 ns
TPSFD_KU11P Setup XCKU11P 1.99 2.28 2.38 3.54 3.79 ns
TPHFD_KU11P Hold –0.38 –0.38 –0.38 –1.05 –1.05 ns
TPSFD_KU13P Setup XCKU13P 1.51 1.79 1.85 2.84 3.05 ns
TPHFD_KU13P Hold –0.04 –0.04 –0.04 –0.60 –0.60 ns
TPSFD_KU15P Setup XCKU15P 2.00 2.29 2.38 3.56 3.83 ns
TPHFD_KU15P Hold –0.38 –0.38 –0.38 –1.08 –1.08 ns
TPSFD_KU19P Setup XCKU19P 0.88 1.03 1.04 1.99 2.13 ns
TPHFD_KU19P Hold 0.51 0.51 0.51 –0.03 –0.03 ns
TPSFD_XQKU5P Setup XQKU5P N/A 2.28 2.38 N/A 3.83 ns
TPHFD_XQKU5P Hold N/A –0.36 –0.36 N/A –1.04 ns
TPSFD_XQKU15P Setup XQKU15P N/A 2.29 2.38 N/A 3.83 ns
TPHFD_XQKU15P Hold N/A –0.38 –0.38 N/A –1.08 ns
  1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
  2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
  3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 2. Global Clock Input Setup and Hold With MMCM
Symbol Description Device Speed Grade and VCCINT Operating Voltages Units
0.90V 0.85V 0.72V
-3 -2 -1 -2 -1
Input Setup and Hold Time Relative to Global Clock Input Signal using SSTL15 Standard. 1, 2, 3
TPSMMCMCC_KU3P Global clock input and input flip-flop (or latch) with MMCM Setup XCKU3P 2.04 2.04 2.16 2.04 2.16 ns
TPHMMCMCC_KU3P Hold –0.17 –0.17 –0.17 –0.23 –0.23 ns
TPSMMCMCC_KU5P Setup XCKU5P 2.04 2.04 2.16 2.04 2.16 ns
TPHMMCMCC_KU5P Hold –0.17 –0.17 –0.17 –0.23 –0.23 ns
TPSMMCMCC_KU9P Setup XCKU9P 2.00 2.00 2.12 2.00 2.12 ns
TPHMMCMCC_KU9P Hold –0.11 –0.11 –0.11 –0.18 –0.18 ns
TPSMMCMCC_KU11P Setup XCKU11P 1.89 1.89 2.02 1.89 2.02 ns
TPHMMCMCC_KU11P Hold –0.20 –0.20 –0.20 –0.25 –0.25 ns
TPSMMCMCC_KU13P Setup XCKU13P 1.99 1.99 2.12 1.99 2.12 ns
TPHMMCMCC_KU13P Hold –0.10 –0.10 –0.10 –0.16 –0.16 ns
TPSMMCMCC_KU15P Setup XCKU15P 1.89 1.89 2.03 1.89 2.03 ns
TPHMMCMCC_KU15P Hold –0.16 –0.16 –0.16 –0.23 –0.23 ns
TPSMMCMCC_KU19P Setup XCKU19P 2.01 2.02 2.13 2.02 2.13 ns
TPHMMCMCC_KU19P Hold –0.09 –0.09 –0.09 –0.18 –0.18 ns
TPSMMCMCC_XQKU5P Setup XQKU5P N/A 2.04 2.16 N/A 2.16 ns
TPHMMCMCC_XQKU5P Hold N/A –0.17 –0.17 N/A –0.23 ns
TPSMMCMCC_XQKU15P Setup XQKU15P N/A 1.89 2.03 N/A 2.03 ns
TPHMMCMCC_XQKU15P Hold N/A –0.16 –0.16 N/A –0.23 ns
  1. Setup and hold times are measured over worst case conditions (process, voltage, temperature). Setup time is measured relative to the global clock input signal using the slowest process, slowest temperature, and slowest voltage. Hold time is measured relative to the global clock input signal using the fastest process, fastest temperature, and fastest voltage.
  2. This table lists representative values where one global clock input drives one vertical clock line in each accessible column, and where all accessible I/O and CLB flip-flops are clocked by the global clock net.
  3. Use IBIS to determine any duty-cycle distortion incurred using various standards.
Table 3. Sampling Window
Description Speed Grade and VCCINT Operating Voltages Units
0.90V 0.85V 0.72V
-3 -2 -1 -2 -1
TSAMP_BUFG 1 510 610 610 610 610 ps
TSAMP_NATIVE_DPA 2 100 100 125 125 150 ps
TSAMP_NATIVE_BISC 3 60 60 85 85 110 ps
  1. This parameter indicates the total sampling error of the Kintex UltraScale+ FPGA DDR input registers, measured across voltage, temperature, and process. The characterization methodology uses the MMCM to capture the DDR input registers' edges of operation. These measurements include: CLK0 MMCM jitter, MMCM accuracy (phase offset), and MMCM phase shift resolution. These measurements do not include package or clock tree skew.
  2. This parameter is the receive sampling error for RX_BITSLICE when using dynamic phase alignment.
  3. This parameter is the receive sampling error for RX_BITSLICE when using built-in self-calibration (BISC).
Table 4. Input Logic Characteristics for Dynamic Phase Aligned Applications (Component Mode)
Description Speed Grade and VCCINT Operating Voltages Units
0.90V 0.85V 0.72V
-3 -2 -1 -2 -1
TINPUT_LOGIC_UNCERTAINTY 1 40 ps
TCAL_ERROR 2 24 ps
  1. Input_logic_uncertainty accounts for the setup/hold and any pattern dependent jitter for the input logic (input register, IDDRE1, or ISERDESE3).
  2. Calibration error associated with quantization effects based on the IDELAY resolution. Calibration must be performed for each input pin to ensure optimal performance.