MMCM Switching Characteristics - DS189

MMCM_F_INMAX

Maximum input clock frequency.

800.00

800.00

800.00

MHz

MMCM_F_INMIN

Minimum input clock frequency.

10.00

10.00

10.00

MHz

MMCM_F_INJITTER

Maximum input clock period jitter.

< 20% of clock input period or 1 ns Max

MMCM_F_INDUTY

Allowable input duty cycle: 10—49 MHz.

25

25

25

%

Allowable input duty cycle: 50—199 MHz.

30

30

30

%

Allowable input duty cycle: 200—399 MHz.

35

35

35

%

Allowable input duty cycle: 400—499 MHz.

40

40

40

%

Allowable input duty cycle: > 500 MHz.

45

45

45

%

MMCM_F_{MIN_PSCLK}

Minimum dynamic phase-shift clock frequency.

0.01

0.01

0.01

MHz

MMCM_F_{MAX_PSCLK}

Maximum dynamic phase-shift clock frequency.

500.00

450.00

450.00

MHz

MMCM_F_VCOMIN

Minimum MMCM VCO frequency.

600.00

600.00

600.00

MHz

MMCM_F_VCOMAX

Maximum MMCM VCO frequency.

1440.00

1200.00

1200.00

MHz

MMCM_F_BANDWIDTH

Low MMCM bandwidth at typical.(1)

1.00

1.00

1.00

MHz

High MMCM bandwidth at typical.(1)

4.00

4.00

4.00

MHz

MMCM_T_{STATPHAOFFSET}

Static phase offset of the MMCM outputs.(2)

0.12

0.12

0.12

ns

MMCM_T_OUTJITTER

MMCM output jitter.

Note 3

MMCM_T_OUTDUTY

MMCM output clock duty-cycle precision.(4)

0.20

0.20

0.20

ns

MMCM_T_LOCKMAX

MMCM maximum lock time.

100.00

100.00

100.00

µs

MMCM_F_OUTMAX

MMCM maximum output frequency.

800.00

800.00

800.00

MHz

MMCM_F_OUTMIN

MMCM minimum output frequency.(5)(6)

4.69

4.69

4.69

MHz

MMCM_T_EXTFDVAR

External clock feedback variation.

< 20% of clock input period or 1 ns Max

MMCM_RST_MINPULSE

Minimum reset pulse width.

5.00

5.00

5.00

ns

MMCM_F_PFDMAX

Maximum frequency at the phase frequency detector.

500.00

450.00

450.00

MHz

MMCM_F_PFDMIN

Minimum frequency at the phase frequency detector.

10.00

10.00

10.00

MHz

MMCM_T_FBDELAY

Maximum delay in the feedback path.

3 ns Max or one CLKIN cycle

MMCM Switching Characteristics Setup and Hold

T_{MMCMDCK_PSEN}/ T_{MMCMCKD_PSEN}

Setup and hold of phase-shift enable.

1.04/0.00

1.04/0.00

1.04/0.00

ns

T_{MMCMDCK_PSINCDEC}/ T_{MMCMCKD_PSINCDEC}

Setup and hold of phase-shift increment/decrement.

1.04/0.00

1.04/0.00

1.04/0.00

ns

T_{MMCMCKO_PSDONE}

Phase shift clock-to-out of PSDONE.

0.68

0.81

0.81

ns

Dynamic Reconfiguration Port (DRP) for MMCM Before and After DCLK

T_{MMCMDCK_DADDR}/ T_{MMCMCKD_DADDR}

DADDR setup/hold.

1.40/0.15

1.63/0.15

1.63/0.15

ns, Min

T_{MMCMDCK_DI}/ T_{MMCMCKD_DI}

DI setup/hold.

1.40/0.15

1.63/0.15

1.63/0.15

ns, Min

T_{MMCMDCK_DEN}/ T_{MMCMCKD_DEN}

DEN setup/hold.

1.97/0.00

2.29/0.00

2.29/0.00

ns, Min

T_{MMCMDCK_DWE}/ T_{MMCMCKD_DWE}

DWE setup/hold.

1.40/0.15

1.63/0.15

1.63/0.15

ns, Min

T_{MMCMCKO_DRDY}

CLK to out of DRDY.

0.72

0.99

0.99

ns, Max

F_DCK

DCLK frequency.

200.00

200.00

200.00

MHz, Max

Notes:

1.​The MMCM does not filter typical spread-spectrum input clocks because they are usually far below the bandwidth filter frequencies.

2.​The static offset is measured between any MMCM outputs with identical phase.

3.​Values for this parameter are available in the Clocking Wizard [Ref 8].

4.​Includes global clock buffer.

5.​Calculated as F_VCO/128 assuming output duty cycle is 50%.

6.​When CLKOUT4_CASCADE = TRUE, MMCM_F_OUTMIN is 0.036 MHz.