Clock Buffers and Networks - Clock Buffers and Networks - DS189

T_{BCCCK_CE}/T_{BCCKC_CE}(1)

CE pins setup/hold.

0.13/0.40

0.16/0.41

0.16/0.41

ns

T_{BCCCK_S}/ T_{BCCKC_S}(1)

S pins setup/hold.

0.13/0.40

0.16/0.41

0.16/0.41

ns

T_{BCCKO_O}(2)

BUFGCTRL delay from I0/I1 to O.

0.09

0.10

0.10

ns

Maximum Frequency

F_{MAX_BUFG}

Global clock tree (BUFG).

628.00

464.00

464.00

MHz

Notes:

1.​T_{BCCCK_CE} and T_{BCCKC_CE} must be satisfied to assure glitch-free operation of the global clock when switching between clocks. These parameters do not apply to the BUFGMUX primitive that assures glitch-free operation. The other global clock setup and hold times are optional; only needing to be satisfied if device operation requires simulation matches on a cycle-for-cycle basis when switching between clocks.

2.​T_{BGCKO_O} (BUFG delay from I0 to O) values are the same as T_{BCCKO_O} values.

T_{BIOCKO_O}

Clock to out delay from I to O.

1.26

1.54

1.54

ns

Maximum Frequency

F_{MAX_BUFIO}

I/O clock tree (BUFIO).

680.00

600.00

600.00

MHz

T_{BRCKO_O}

Clock to out delay from I to O.

0.76

0.99

0.99

ns

T_{BRCKO_O_BYP}

Clock to out delay from I to O with Divide Bypass attribute set.

0.39

0.52

0.52

ns

T_{BRDO_O}

Propagation delay from CLR to O.

0.85

1.09

1.09

ns

Maximum Frequency

F_{MAX_BUFR}(1)

Regional clock tree (BUFR).

375.00

315.00

315.00

MHz

Notes:

1.​The maximum input frequency to the BUFR is the BUFIO F_MAX frequency.

T_{BHCKO_O}

BUFH delay from I to O.

0.11

0.13

0.13

ns

T_{BHCCK_CE}/ T_{BHCKC_CE}

CE pin setup and hold.

0.22/0.15

0.28/0.21

0.28/0.21

ns

Maximum Frequency

F_{MAX_BUFH}

Horizontal clock buffer (BUFH).

628.00

464.00

464.00

MHz

T_{DCD_CLK}

Global clock tree duty-cycle distortion.(1)

All

0.20

0.20

0.20

ns

T_CKSKEW

Global clock tree skew.(2)

XC7S6

0.05

0.06

0.06

ns

XC7S15

0.05

0.06

0.06

ns

XC7S25

0.26

0.26

0.26

ns

XC7S50

0.26

0.26

0.26

ns

XC7S75

0.33

0.36

0.36

ns

XC7S100

0.33

0.36

0.36

ns

XA7S6

0.05

0.06

N/A

ns

XA7S15

0.05

0.06

N/A

ns

XA7S25

0.26

0.26

N/A

ns

XA7S50

0.26

0.26

N/A

ns

XA7S75

0.33

0.36

N/A

ns

XA7S100

0.33

0.36

N/A

ns

T_{DCD_BUFIO}

I/O clock tree duty cycle distortion.

All

0.14

0.14

0.14

ns

T_BUFIOSKEW

I/O clock tree skew across one clock region.

All

0.03

0.03

0.03

ns

T_{DCD_BUFR}

Regional clock tree duty cycle distortion.

All

0.18

0.18

0.18

ns

Notes:

1.​These parameters represent the worst-case duty cycle distortion observable at the I/O flip flops. For all I/O standards, IBIS can be used to calculate any additional duty cycle distortion that might be caused by asymmetrical rise/fall times.

2.​The T_CKSKEW value represents the worst-case clock-tree skew observable between sequential I/O elements. Significantly less clock-tree skew exists for I/O registers that are close to each other and fed by the same or adjacent clock-tree branches. Use the Xilinx timing analysis tools to evaluate clock skew specific to your application.