Revision History - 4.2 English

Zynq 7000 SoC and 7 Series Devices Memory Interface Solutions LogiCORE IP Data Sheet (DS176)

Document ID
DS176
Release Date
2024-05-30
Version
4.2 English

The following table shows the revision history for this document.

Section Revision Summary
05/30/2024 Version 4.2
All sections Vivado Design Suite release for MIG v4.2.
12/05/2018 Version 4.2
All sections Vivado Design Suite release for MIG v4.2.
04/04/2018 Version 4.1
All sections Vivado Design Suite release for MIG v4.1.
03/02/2018 Version 4.1
All sections Reverted doc version to v4.1 to match Vivado Design Suite release for MIS core v4.1.
10/04/2017 Version 4.2
All sections Vivado Design Suite release for MIG v4.2.
Features Added QDR II+ density device support.
RLDRAM II Features Added RLDRAM II density device support.
RLDRAM 3 Features Added RLDRAM 3 density device support.
06/07/2017 Version 4.2
All sections Vivado Design Suite release for MIG v4.2. Added Spartan 7 support and changed it to 7 series family.
04/05/2017 Version 4.2
All sections Vivado Design Suite release for MIG v4.2.
11/30/2016 Version 4.1
All sections Vivado Design Suite release for MIG v4.1.
10/05/2016 Version 4.1
All sections Vivado Design Suite release for MIG v4.1.
06/08/2016 Version 4.0
All sections Vivado Design Suite release for MIG v4.0.
04/06/2016 Version 3.0
All sections Vivado Design Suite release for MIG v3.0.
11/18/2015 Version 2.4
All sections Vivado Design Suite release for MIG v2.4.
09/30/2015 Version 2.4
All sections Vivado Design Suite release for MIG v2.4.
AXI4 Slave Interface Features Added 72 bits with eight bits of ECC.
06/24/2015 Version 2.3
All sections Vivado Design Suite release for MIG v2.3.
04/01/2015 Version 2.3
All sections Vivado Design Suite release for MIG v2.3.
Resource Utilization Updated table.
11/19/2014 Version 2.3
All sections Vivado Design Suite release for MIG v2.3.
10/01/2014 Version 2.2
All sections Vivado Design Suite release for MIG v2.2.
06/04/2014 Version 2.1
All sections Vivado Design Suite release for MIG v2.1.
Resource Utilization Updated table.
12/18/2013 Version 2.0
All sections Vivado Design Suite release for MIG v2.0. Updated doc title.
10/02/2013 Version 2.0
All sections Vivado Design Suite release for MIG v2.0.
IP Facts Updated simulation.
06/19/2013 Version 2.0
All sections Vivado Design Suite release for MIG v2.0. Revision number advanced to 2.0 to align with core version number.
03/20/2013 Version 1.8
All sections ISE 14.5 and Vivado Design Suite release for MIG v1.9.
Resource Utilization
  • Moved Resource table into a separate Resource section.
  • Updated 7 Series FPGAs DDR3 SDRAM in Resource Utilization table. Added LPDDR2 SDRAM content.
12/18/2012 Version 1.7
All sections ISE 14.4 and Vivado Design Suite release for MIG v1.8. Added 8 Gb to DDR3 SDRAM feature. Added VHDL support.
10/16/2012 Version 1.6
All sections ISE 14.3 and Vivado Design Suite release for MIG v1.7. Added RLDRAM 3 content.
07/25/2012 Version 1.5
All sections ISE 14.2 and Vivado Design Suite release for MIG v1.6.
04/24/2012 Version 1.4
All sections ISE 14.1 and Vivado Design Suite release for MIG v1.5. Added VHDL source code for top-level files for all memory devices. For DDR3 and DDR2 SDRAM, added: I/O Power Reduction option, AXI4-Lite interface support for ECC control and status registers, and 72-bit data width.
01/18/2012 Version 1.3
All sections ISE 13.4 and Vivado Design Suite release for MIG v1.4. For DDR3 SDRAM: Added support for 4 Gb density, DDR3L (1.35 V), and dual rank UDIMM, RDIMM, and SODIMM. Removed support for AXI4-Lite interface and 72-bit data width. Added DDR2 SDRAM support.
10/19/2011 Version 1.2
All sections ISE 13.3 and Vivado Design Suite release for MIG v1.3. Added Resources to the IP Facts table. For DDR3 SDRAM, added support for up to eight controllers, added 2:1 as an interface clock ratio, added AXI4-Lite interface support, and added 72 as a memory data width option. For QDR II+ SRAM, added support for 2-word bursts and support for up to eight controllers. For RLDRAM II, added support for Address Multiplexing Mode and support for up to eight controllers.
06/22/2011 Version 1.1
All sections ISE 13.2 software release. Added RLDRAM II support throughout document. Added single rank UDIMM support bullet to DDR3 SDRAM Features. Added internal VREF support.
03/01/2011 Version 1.0
Initial release. N/A