Resource Utilization - 4.2 English

Zynq 7000 SoC and 7 Series Devices Memory Interface Solutions LogiCORE IP Data Sheet (DS176)

Document ID
DS176
Release Date
2024-05-30
Version
4.2 English
Table 1. Resource Utilization for 7 Series FPGAs
Product 1 LUTs Flip-Flops BUFG PLLE2 MMCM Block RAM
7 series FPGAs DDR3 SDRAM 2 14,016 9,019 4 3, 4 1 2 3 2
7 series FPGAs DDR2 SDRAM 2 9,267 6,038 2 1 1 0
7 series FPGAs QDR II+ SRAM 3,209 2,568 2 1 1 0
7 series FPGAs RLDRAM II 6,261 4,519 2 1 1 7
7 series FPGAs RLDRAM 3 9,039 7,950 2 1 1 12
7 series FPGAs LPDDR2 SDRAM 3,952 3,285 2 1 1 0
  1. Resource utilization can change depending on the options chosen, memory device used, or both. Resource information is provided for 72-bit DDR3 SDRAM, 72-bit DDR2 SDRAM, 36-bit QDR II+ SRAM, 72-bit RLDRAM II, 72-bit RLDRAM 3, and 32-bit LPDDR2 SDRAM interfaces.
  2. UDIMM 72-bit designs (ECC disabled).
  3. For design frequencies > 667 MHz, three BUFGs and two MMCM are used in the design. For design frequencies < 667 MHz, only two BUFGs and one MMCM are used in the design.
  4. One BUFG used for the clock during write calibration.