- RLDRAM II common I/O (CIO) memory device support
- x18 and x36 memory width support
- 288 Mb and 576 Mb density device support
- Configurable data bus widths (x18, x36, x72)
- 4-word and 8-word burst support
- Configuration 1, 2, 3 support
- Address Multiplexing Mode support
- ODT support
- Source code delivery in Verilog and VHDL (top-level files only)
- 2:1 memory to FPGA logic interface clock ratio
- Internal VREF support
- Multicontroller support for up to eight controllers