RLDRAM 3 Features - 4.2 English

Zynq 7000 SoC and 7 Series Devices Memory Interface Solutions LogiCORE IP Data Sheet (DS176)

Document ID
DS176
Release Date
2024-05-30
Version
4.2 English
  • x18 and x36 memory width support
  • 576 Mb and 1152 Mb density device support
  • Configurable data bus widths (x18, x36, x72)
  • 2-word, 4-word, and 8-word burst support
  • Address Multiplexing Mode support
  • ODT support
  • Source code delivery in Verilog only
  • 4:1 memory to FPGA logic interface clock ratio
  • Internal VREF support