IP Facts - 4.2 English

Zynq 7000 SoC and 7 Series Devices Memory Interface Solutions LogiCORE IP Data Sheet (DS176)

Document ID
DS176
Release Date
2024-05-30
Version
4.2 English
AMD LogiCORE™ IP Facts Table
Core Specifics
Supported Device Family 1 Zynq 7000 SoC, 7 series 2 FPGAs
Supported Memory DDR3 Component and DIMM, DDR2 Component and DIMM, QDR II+, RLDRAM II, RLDRAM 3, and LPDDR2 SDRAM Components
Resources See Resource Utilization
Provided with Core
Documentation Product Specification User Guide
Design Files Verilog, VHDL (top-level files only)
Example Design Verilog, VHDL (top-level files only)
Test Bench N/A
Constraints File XDC
Supported S/W Driver N/A
Tested Design Flows 3
Design Entry AMD Vivado™ Design Suite
Simulation For supported simulators, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).
Synthesis 4 Vivado Synthesis
Support
Release Notes and Known Issues Master Answer Record: 75889
All Vivado IP Change Logs Master Vivado IP Change Logs: 72775
Support web page
  1. For a complete listing of supported devices, see the release notes for MIG.
  2. See the Virtex 7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS183), the Kintex 7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS182), or Spartan 7 FPGAs Data Sheet: DC and AC Switching Characteristics (DS189) for performance information.
  3. For the supported versions of the tools, see the Vivado Design Suite User Guide: Release Notes, Installation, and Licensing (UG973).
  4. The standard synthesis flow for Synplify is not supported for the core.