As shown in the figure, the top-level functional blocks of the 7 series FPGAs memory interface solution include:
- The User Interface block:
- Presents the user interface to a user design
- Provides a simple and user-friendly alternative to the native interface
- Buffers read and write data
- Reorders read return data to match the request order
- Presents a flat address space and translates it to the addressing required by the SDRAM
- The Memory Controller block:
- Receives requests from the user design
- Reorders requests to minimize dead states for maximum SDRAM performance
- Manages SDRAM row/bank configuration
- Performs high-level SDRAM management such as refresh and activate/precharge
- The Physical Layer (PHY) block:
- Interfaces with the Memory Controller block over a simple interface and translates the signals into the actual signals sent to the SDRAM, and vice versa.
- Translates and synchronizes control and data over various clock domains
- Initializes the SDRAM
- Performs calibration to center align capture clocks with read data
The figure also shows a user design connecting to the memory interface. For more details regarding the design, see the Zynq 7000 SoC and 7 series Devices Memory Interface Solutions (UG586) provided with the core.