- Component support for interface widths up to 32 bits
- 2 and 4 Gb density device support
- 8-bank support
- x16 and x32 device support
- 8:1 DQ:DQS ratio support
- 8-word burst support
- JEDEC-compliant LPDDR2 SDRAM initialization support
- Source code delivery in Verilog
- 2:1 memory to FPGA logic interface clock ratio
- Internal VREF support
- Two controller request processing modes:
- Normal: reorder requests to optimize system throughput and latency
- Strict: memory requests are processed in the order received