- Component support for interface widths up to 72 bits
- Single and dual rank UDIMM, RDIMM, and SODIMM support
- DDR3 (1.5V) and DDR3L (1.35V)
- 1, 2, 4, and 8 Gb density device support
- 8-bank support
- x8 and x16 device support
- 8:1 DQ:DQS ratio support
- Configurable data bus widths (multiples of 8, up to 72 bits)
- 8-word burst support
- Support for 5 to 14 cycles of column-address strobe (CAS) latency (CL)
- On-die termination (ODT) support
- Support for 5 to 10 cycles of CAS write latency
- ZQ calibration – initial and periodic (configurable)
- Write leveling support for DDR3 (fly-by routing topology required for DDR3 component designs)
- JEDEC®-compliant DDR3 initialization support
- Source code delivery in Verilog and VHDL (top-level files only)
- 4:1 and 2:1 memory to FPGA logic interface clock ratio
- ECC support
- I/O Power Reduction option reduces average I/O power by automatically disabling DQ/DQS IBUFs and internal terminations during writes and periods of inactivity
- Internal VREF support
- Multicontroller support for up to eight controllers
- Two controller request processing modes:
- Normal: reorder requests to optimize system throughput and latency
- Strict: memory requests are processed in the order received