DDR2 SDRAM Features - 4.2 English

Zynq 7000 SoC and 7 Series Devices Memory Interface Solutions LogiCORE IP Data Sheet (DS176)

Document ID
Release Date
4.2 English
  • Component support for interface widths up to 64 bits
  • Single rank UDIMM, RDIMM, and SODIMM
  • 1 and 2 Gb density device support (additional densities supported in the MIG tool using the Create Custom Part feature)
  • 4- and 8-bank support
  • x8 and x16 device support
  • 8:1 DQ:DQS ratio support
  • Configurable data bus widths (multiples of 8, up to 72 bits)
  • 8-word burst support
  • Support for 3 to 6 cycles of column address strobe (CAS) latency
  • On-die termination (ODT) support
  • JEDEC-compliant DDR2 initialization support
  • Source code delivery in Verilog and VHDL (top-level files only)
  • 4:1 and 2:1 memory to FPGA logic interface clock ratio
  • ECC support
  • I/O Power Reduction option reduces average I/O power by automatically disabling DQ/DQS IBUFs and internal terminations during writes and periods of inactivity
  • Internal VREF support
  • Two controller request processing modes:
    • Normal: Reorder requests to optimize system throughput and latency
    • Strict: Memory requests are processed in the order received
  • Multiple controllers per FPGA supported running the MIG tool multiple times