Typical applications for the 7 series FPGAs memory interface solutions include LPDDR2 SDRAM interfaces.
The following figure shows a high-level block diagram of the 7 series FPGAs memory interface solution connecting a user design to a LPDDR2 SDRAM device. The physical layer (PHY) side of the design is connected to the LPDDR2 SDRAM device through FPGA I/O blocks (IOBs), and the user interface side is connected to the user design through FPGA logic. For more details regarding the design, see the Zynq 7000 SoC and 7 series Devices Memory Interface Solutions (UG586) provided with the core.
Figure 1. LPDDR2 SDRAM Memory Interface Solution
